M. Notten

A 48-860MHz digital cable tuner IC with integrated RF and IF selectivity

A single-chip digital cable tuner with an active splitter for cable data modems and set-top boxes is realized in a 0.5/spl mu/m, 30GHz BiCMOS technology. The IC employs a single down-conversion, low-IF architecture and can receive signals in the 48-860MHz range. Fully integrated selectivity is obtained in combination with a channel decoder. Power consumption is 1.5W with a 3.3V supply.

60GHz quadrature signal generation with a single phase VCO and polyphase filter in a 0.25μm SiGe BiCMOS technology

This paper describes a single-phase VCO followed by a polyphase filter to generate 60 GHz quadrature signals. The IC is implemented in a SiGe:C-BiCMOS process. A quadrature down-conversion mixer is included for accurate evaluation of I/Q-matching. The RF inputs of the mixers are driven via an on-chip passive power splitter. The VCO exhibits a tuning range between 59.5-61.5 GHz and a phase noise of -92 dBc/Hz at 1 MHz offset from the carrier. The measured I/Q-matching of 28.6 dB corresponds to a phase error of 4.2deg. The power consumption of the IC including the mixers is 150 mW at a supply voltage of 4.5 V and the chip area including bondpads is 1 mm2.

Antenna and input stages of a 470-710 MHz silicon TV tuner for portable applications

This paper describes the antenna and input stages of a silicon TV-tuner intended for portable devices such as cell phones, laptops and PDAs. The tuner meets the requirements of the mobile and portable DVB-T radio access interface specifications MBRAI. The first stages of the tuner comprise a broadband antenna, a matching and filtering circuit, and LNA. The frequency band of operation is 470-710MHz (DVB-H). The matching and filtering circuitry comprises a strong GSM trap that attenuates the GSM frequencies by more than 40dB. The overall power gain is 20 /spl plusmn/ 3dB in the band, and the NF of the total chain is less than 4dB. The power consumption is 21mW from 2.5V supply. The LNA is fabricated in a 0.25/spl mu/m, 35GHz f/sub T/ BiCMOS technology based on D. Szmyd et al. (2001).

A 48-860 MHz TV splitter amplifier exhibiting an IIP2 and IIP3 of 94dBmV and 73dBmV

This paper describes a 48-860 MHz TV splitter amplifier with three outputs, based on a negative feedback design. The amplifier is intended for TV, VCR and set-top box (STB) applications, where multiple tuners have to be connected to the same cable outlet. The amplifier compromises high linearity and low noise figure by controlling its gain. At a frequency of 850 MHz, the input IP2 and IP3 are 94 dBmV and 73 dBmV, respectively, for the lowest gain setting while the noise figure is 7 dB for the highest gain setting. The design is fabricated in a 0.5 /spl mu/m, 30 GHz BiCMOS technology and dissipates 130 mW from a 3.3 V supply.

A low-IF CMOS double quadrature mixer exhibiting 58 dB of image rejection for silicon TV tuners

To ease full integration of a TV-receiver, a low-IF architecture has been developed. To cancel the adjacent channel at the image of the mixer, a quadrature mixer can be used with a limited image rejection of about 40 dB, which is 10 dB below the target of more than 50 dB. Therefore, a low-IF passive CMOS double quadrature mixer has been implemented which achieves high dynamic range and more than 58 dB of image rejection over a wide frequency range. The image rejection is now limited by the mismatch in the mixers and the IF polyphase filter.

Low Noise Amplifier with Integrated Balun for 24GHz Car Radar

This paper discusses the design, simulation and measurement results of a single-ended to differential Low Noise Amplifier (LNA) for 24 GHz short range car radar applications in a production 0.25 mum SiGe:C-BiCMOS technology [1]. The input and two single-ended outputs are designed for 50 Omega impedance. The LNA achieves a measured 13.2 dB gain and 4.2dB noise figure at 24 GHz. Simulations and measurements are in close agreement. The achieved gain and noise figure are as good as for an earlier reported fully single-ended LNA [2]. No balun is required. The 0.55 x 0.60 mm IC dissipates 40 mW from a 3.3 V supply.

A CMOS quadrature down-conversion mixer with analog I/Q correction obtaining 55 dB of image rejection for TV on mobile applications

An analog I/Q correction system has been developed to lower the power consumption of a quadrature mixer in a silicon TV-tuner intended for mobile applications. The image rejection of this mixer is limited to about 40 dB and the target is 57 dB. The passive CMOS quadrature mixer with I/Q correction is realized, achieving the matching properties of a double quadrature mixer and obtaining more than 55 dB of image rejection and a high dynamic range over a wide frequency range consuming 27mW at 2.7V

Distributed de-embedding technique for accurate on-chip passive measurements based on Open-Short structures

This paper demonstrates a distributed de-embedding technique to derive accurate models for on-chip passives. Due to the inherently large pitch of on-wafer probes, interconnect lengths between bondpads and the device under test (DUT) of several hundreds of µm are often unavoidable for inductors and transmission lines. At frequencies above 10GHz, the length of such interconnects becomes significant with respect to the wavelength. The impedance transformation through the lines between DUT and bondpads is not taken into account in the standard Open-Short de-embedding technique. Moreover, the impedance of the open de-embedding is lumped to a single parallel impedance located at the bondpad. This approach is not accurate at frequencies above 10GHz. Distributed techniques are known that improve accuracy. However, these require the use of dedicated transmission line de-embedding structures. In this paper, a method is demonstrated to derive a transmission line de-embedding model from standard Open-Short de-embedding structures. The sub-optimum de-embedding design showed a slowing factor of √(11) which was due to regular holes in the metal shield underneath the signal lines. Guidelines for the design of optimum de-embedding structures are provided.

A low-IF bipolar double-quadrature mixer exhibiting 53 dB of image rejection [TV tuner application]

This paper presents a bipolar double quadrature mixer with more than 53 dB of image rejection and consuming 115 mW. This IC has been developed to reduce the power consumption in a fully integrated low-IF TV tuner.

60GHz VCOs with transmission line resonator in a 0.25μm SiGe BiCMOS technology

In this paper, two 60 GHz LC-VCOs are compared. The varactorless oscillators are identical except for the implementation of the inductors. One oscillator uses a traditional spiral inductor, the other oscillator uses a shorted transmission line as inductor. Although the spiral inductor is favorable in terms of quality factor and self-resonant frequency, the shorted transmission line offers superior isolation from the substrate. The solid ground shield of the transmission line offers reduced sensitivity to substrate interference. The 60 GHz VCO with shorted transmission line as inductor achieves a measured 22.6 dB lower power level of the main oscillator sideband for a given interference level. The experiment is performed in a BiCMOS process, but the results are also applicable to CMOS technologies.