M. O. Alam

Modelling methodology for thermal analysis of hot solder dip process

The shift of electronics industry towards the use of lead-free solders in components manufacturing brought also the challenge of addressing the problem of tin whiskers. Manufacturers of high reliability and safety critical equipment in sectors such as defence and aerospace rely increasingly on the use of commercial-of-the-shelf (COTS) electronic components for their products and systems. The use of COTS components with lead-free solder plated terminations comes with the risks for their long term reliability associated with tin whisker growth related failures. In the case of leaded type electronic components such as Quad Flat Package (QFP) and Small Outline Package (SOP), one of the promising solutions to this problem is to “re-finish” the package terminations by replacing the lead-free solder coatings on the leads with conventional tin–lead solder. This involves subjecting the electronic components to a post-manufacturing process known as Hot Solder Dip (HSD). One of the main concerns for adopting HSD (refinishing) as a strategy to the tin whisker problem is the potential risk for thermally induced damage in the components when subjected to this process. n nThis paper details a thermal modelling driven approach to the characterisation of the impact of hot solder dipping on electronic components. Main focus is on the evaluation of the re-finishing process effects on parts’ temperature gradients and heating/cooling rates, and on the advantages of applying an efficient model based process optimisation. Transient thermal finite element analysis is used to evaluate the temperature distribution in Quad Flat Package (QFP) variants during a double-dip hot solder dipping process developed by Micross Components Ltd. Full detailed three-dimensional (3D) models of the components are developed using comprehensive characterisation of the respective package structures and materials based on X-ray, SEM-EDX, cross-sectional metallurgy and 3D CT scan. The thermal modelling approach is validated using thermocouple measurement data for one of the studied parts and by comparing with model temperature predictions. Model results have informed the process optimisation strategy, and through experimentation key process parameters are alerted to provide optimal thermal characteristics. The optimised process settings result in temperature ramp rates at die level within recommended manufacture’s limit. A demonstration and discussion on the influence of the package internal structure and design on the thermal response to HSD is also provided.

Finite-Element Simulation of Stress Intensity Factors in Solder Joint Intermetallic Compounds

The trend toward the miniaturization of electronic products leads to the need for very small sized solder joints, where the volume fraction of intermetallic compounds (IMCs) would be higher. In this paper, a fracture mechanics study of the IMC layer for SnPb and Pb-free solder joints has been carried out using a finite-element numerical computer modeling method. It is assumed that only one crack is present in the IMC layer. The linear elastic fracture mechanics approach is used for the parametric study of the stress intensity factors [(SIFs) K I and K II ] at the predefined crack in the IMC layer of the solder-butt-joint tensile sample. Contrary to intuition, it is revealed that a thicker IMC layer, in fact, increases the reliability of a solder joint for a cracked IMC-assuming that there is only a single crack that exists in the IMC layer. Even if the whole solder layer is replaced by the IMC in the solder joint, the fracture propagation possibility is greatly reduced. Values of K I and K II are found to decrease with the location of the crack farther away from the solder interfaces while other parameters are constant. Temperature and strain rate are also found to have a significant influence on the SIF values. It has been found that a soft solder matrix generates a nonuniform plastic deformation across the solder-IMC interface near the crack tip that is responsible for obtaining a wide range of K I and K II values.

Study of the thermal stress in a Pb-free half-bump solder joint under current stressing

The thermal stress in a Sn3.5Ag1Cu half-bump solder joint under a 3.82×108A∕m2 current stressing was analyzed using a coupled-field simulation. Substantial thermal stress accumulated around the Al-to-solder interface, especially in the Ni+(Ni,Cu)3Sn4 layer, where a maximal stress of 138MPa was identified. The stress gradient in the Ni layer was about 1.67×1013Pa∕m, resulting in a stress migration force of 1.82×10−16N, which is comparable to the electromigration force, 2.82×10−16N. Dissolution of the Ni+(Ni,Cu)3Sn4 layer, void formation with cracks at the anode side, and extrusions at the cathode side were observed.

Fracture mechanics analysis of cracks in solder joint Intermetallic Compounds

The trend towards miniaturization of electronic products leads to the need for very small sized solder joints. Therefore, there is a higher reliability risk that too large a fraction of solder joints will transform into Intermetallic Compounds (IMCs) at the solder interface. In this paper, fracture mechanics study of the IMC layer for SnPb and Pb-free solder joints was carried out using finite element numerical computer modelling method. It is assumed that only one crack is present in the IMC layer. Linear Elastic Fracture Mechanics (LEFM) approach is used for parametric study of the Stress Intensity Factors (SIF, KI and KII), at the predefined crack in the IMC layer of solder butt joint tensile sample. Contrary to intuition, it is revealed that a thicker IMC layer in fact increases the reliability of solder joint for a cracked IMC. Value of KI and KII are found to decrease with the location of the crack further away from the solder interfaces while other parameters are constant. Solder thickness and strain rate were also found to have a significant influence on the SIF values. It has been found that soft solder matrix generates non-uniform plastic deformation across the solder-IMC interface near the crack tip that is responsible to obtain higher KI and KII.

Assessment of refinishing processes for electronic components in high reliability applications

Refinishing of electronics components, also known as hot solder dip (HSD), is sequence of process steps used to remove original solder alloy coatings from package terminations and replacing the finishes with different type of solder composition. Typically this transformation is from lead-free to eutectic tin-lead solder and aims primarily at mitigating the risk of tin whiskers induced failures. Hot solder dip process is the only practical solution for Aerospace, Defence and High Performance (ADHP) industries which are exempt from lead-free legislations and therefore can adopt this post-manufacturing practice as a strategy for making commercial-of-the-shelf (COTS) components usable in electronics assemblies with high reliability and critical safety requirements. Hot solder dipping has a thermal impact on processed components. Assessing the thermo-mechanical response of components to the refinishing process and their susceptibility to damage is an issue of critical importance. This paper presents the scope of a comprehensive experimental study that aimed at assessing the impact of the thermal shock induced from double dip hot solder dip process on different component types and reports on the findings in relation to their vulnerability and subsequent long-term reliability.

Statistical analysis of the impacts of refinishing process on the reliability of microelectronics components

Tin-whisker induced failures have been one of the major concerns of using electronic components with Sn or Sn-rich lead free solder coated I/Os. In some applications, this risk can be mitigated by refinishing the lead-free finishes with conventional tin-lead coatings using a solder dipping process. However, the solder dipping process does not come without reliability risks of its own. In this paper, the impacts of a refinishing process on the reliability of microelectronics components were statistically studied by comparing the electrical test data measured from refinished samples with those of not-refinished. A hot solder dipping (HSD) process was used and all the samples (not-refinished and refinished) were subjected to environmental test conditions of 150 cycles -65/150°C thermal cycling followed by 500 hours 85%RH/85°C humidity test. Electrical testing was designed to measure the current in reverse or zero bias conditions as currents in these regimes would have a measurable increase if moisture ingress occurs. A data reduction process, in conjunction with statistical hypothesis testing, was used to analyze the electrical test data and the results showed that there was no significant difference between the measured currents of post-aged refinished samples and not-refinished ones. Therefore it was concluded that the refinishing process did not have a significant impact on the reliability performance of the tested components.

Shear Strength Analysis of Ball Grid Array (BGA) Solder Interfaces

Ball shear test is the most common test method used to assess the reliability of bond strength for ball grid array (BGA) packages. In this work, a combined experimental and numerical study was carried out to realize of BGA solder interface strength. Solder mask defined bond pads on the BGA substrate were used for BGA ball bonding. Different bond pad metallizations and solder alloys were used. Solid state aging at 150degC up to 1000 h has been carried out to change the interfacial microstructure. Cross-sectional studies of the solder-to-bond pad interfaces was conducted by scanning electron microscopy (SEM) equipped with an energy dispersive X-ray (EDX) analyzer to investigate the interfacial reaction phenomena. Ball shear tests have been carried out to obtain the mechanical strength of the solder joints and to correlate shear behaviour with the interfacial reaction products. An attempt has been taken to realize experimental findings by Finite Element Analysis (FEA). It was found that intermetallic compound (IMC) formation at the solder interface plays an important role in the BGA solder bond strength. By changing the morphology and the microchemistry of IMCs, the fracture propagation path could be changed and hence, reliability could be improved.

Modelling Technologies and Applications

Numerical modelling technology and software is now being used to underwrite the design of many microelectronic and microsystems components. The demands for greater capability of these analysis tools are increasing dramatically, as the user community is faced with the challenge of producing reliable products in ever shorter lead times.

Experimental and modelling study on the effects of refinishing lead-free microelectronic components

Hot Solder Dip (HSD) of electronic components originally manufactured with lead-free solder finishes is seen as a potential solution for making these components available and used in high reliability and critical safety equipment. In this process, also referred as “refinishing”, tin and tin-reach alloy coatings on package terminations are replaced with tin-lead solder thus reducing the risk of failures caused by tin whisker growth. Characterising the effect of HSD process on refinished components from thermo-mechanical point of view is critical. This paper details the findings of an integrated experimental and modelling study that aimed at assessing the impact of the thermal shock induced from HSD on several different Quad Flat Package (QFP) variants and in relation to their subsequent long-term reliability.

Introduction to adhesives joining technology for electronics

Abstract: Polymer adhesives are now considered as invaluable materials for modern-day, low-cost miniaturized consumer electronic products because of their low cost and high production throughput. This introductory chapter describes the different types of adhesives that are used in electronic packaging along with a brief introduction to electronic assemblies and the uses of adhesives in electronics.