M. Santhi

Design and implementation of pipelined MB-OFDM UWB transmitter backend modules on FPGA

In this paper, novel ideas have been proposed for designing and implementing the pipelined MB-OFDM UWB transmitter Digital Backend Modules on FPGA for a data rate of 200 Mbps. The various digital backend modules are scrambler, convolutional encoder, puncturer, interleaver, QPSK mapping, and OFDM. The most critical block is the OFDM block because it consists of 128 point IFFT, that to work at a speed of 528 MHz. This is achieved in the proposed OFDM module by using modified radix-24 SDF algorithm with extensive pipelining of LPM without using parallel architecture. By the way the speed 528 MHz can be obtained with minimum hardware. Also the hardware complexity has been significantly reduced by usage of constant coefficient canonical signed digit (CSD) multipliers and accuracy has been improved by the internal word length maintained at 13 bits which is 7 bits more than the input. For designing the interleaver, the initial problem faced was that the amount of registers that has to be used in designing the interleaver using bit mapping. This leads to thousands of registers in use. In the proposed interleaver, two different RAM banks which are working in tandem with different write and read addresses and clock rates are used to provide optimum results. The implementation has been performed on ALTERA STRATIX III EP3SL50F484C2 FPGA and results obtained are compliance to IEEE 802.15.3a standard.

Synchronous pipelined two-stage radix-4 200Mbps MB-OFDM UWB Viterbi decoder on FPGA

This paper proposes novel techniques for the synchronous pipelined two-stage radix-4 Viterbi decoder for 200Mbps MB-OFDM UWB on FPGA. MB-OFDM UWB requires rate-1/3, 64-state Viterbi decoder to be implemented with 200Mbps data rate and low power. To obtain low power, traceback method is used instead of register exchange method and to obtain high speed, radix-4 Viterbi decoder with two stages is used. Previous paper implemented two-stage, radix-4 Viterbi decoder on ASIC uses 3 pointer algorithm for decoding. In this paper, 2-pointer algorithm which reduces memory requirement compared to 3 pointer algorithm is implemented on FPGA. Also pipelining and LPM modules from ALTERA FPGA are used to achieve more speed. The proposed approach is implemented on ALTERA STRATIX III EP3SE80F1152C2 device and the speed achieved is 68.56MHz with the throughput rate of 274Mbps. In ASIC the module can be operated three times faster than FPGA.

A Novel Pseudo 4-Phase Dual-Rail Asynchronous Protocol with Self-Reset Logic & Multiple-Reset

paper presents a novel pseudo 4-phase dual-rail protocol with self-reset logic suited for high speed asynchronous applications. The traditional 4-phase dual-rail requires the input to be of alternating valid and empty cycles. However the proposed pseudo 4-phase involves continuous stream of valid data without a separate empty cycle. The empty phase is generated internally so that the next valid data can be processed. Also self-reset logic for dual-rail protocol has been proposed in which the combinational blocks resets itself whenever its evaluation phase is completed and the data is latched at the pipeline register. The concept of multiple-reset i.e. resetting each of the gates in the combinational block between any two pipeline registers simultaneously has been introduced reducing the reset phase and hence increasing the throughput rate. An asynchronous 8-bit pipelined carry propagate adder was implemented in 0.18μm technology. The reset phase has reduced by 63.25% and 47.63% compared to the design without self and multiple reset for logic depth of three and two respectively. The results show that the reset phase varies inversely with the logic depth for the proposed design.

FPGA based asynchronous pipelined viterbi decoder using two phase bundled-data protocol

In this paper a novel approach is proposed for the implementation of asynchronous pipelined circuits. In this approach, Synchronous FPGAs form Xilinx and Altera are used for implementing the asynchronous pipelined Circuits using two phase bundled data protocol. Asynchronous pipelined circuits have many potential advantages over their synchronous equivalents including lower latency, lower power consumption, high throughput, avoiding clock skew problem, etc., In this proposed approach, Muller C-element is used to generate the control signals in the handshaking circuit and Double Edge Triggered D-flip-flop (DETDFF) is used to ensure the two phase operation of the control signal generation. To verify the efficacy of this approach, an asynchronous pipelined 4 state, frac12-rate viterbi decoder is implemented on Cyclone II FPGA using Quartus II Altera tool. The throughput of asynchronous pipelined Viterbi decoder using the proposed approach is 181Mbps which is 2.83 times greater than that of the synchronously pipelined Viterbi decoder with 35% increase in area.

Design and FPGA realization of MC-CDMA system using pseudo chaotic sequence generator

A novel chaotic spreading sequences for Multi-carrier code division multiple access (MC-CDMA) system is proposed. DS-CDMA is a type of spread-spectrum communication system in which multiple signal channels occupy the same frequency band, been distinguished by the use of different spreading codes. Implementation of Multi carrier CDMA transmitter and receiver using pseudo chaotic sequences for spreading digital data using Field Programmable Gate Array (FPGA) has been proposed in this paper. The generated pseudo-chaotic sequences are investigated for auto-correlation, cross-correlation and balance properties. The Bit error rate (BER) performance of the system is evaluated in multi-user environment under AWGN channel and reveals that the MC-CDMA system using pseudo-chaotic sequences as spreading sequences significantly outperforms the conventional PN sequences.

FPGA IMPLEMENTATION OF RSEPD TECHNIQUE BASED IMPULSE NOISE REMOVAL

In the process of signals transmission and acquisition, image signals might be corrupted by impulse noise. Generally, digital images are corrupted by impulse noises. These are short duration noises, which degrade an image and are randomly distributed over the image. An efficient FPGA implementation for removing impulse noise in an image is presented in this paper. Existing techniques use standard median filter. These existing approaches changes the pixel values of both noise less and noisy pixels, so image might be blurred in nature. To avoid the changes on noise less pixels, an efficient FPGA implementation of Simple Edge Preserved De-noising technique (SEPD) and Reduced Simple Edge Preserved De-noising technique (RSEPD) are presented in this paper. In this technique, noise detection and noise removal operations are performed. This VLSI design gives better image quality. For 10 percentage noise added image, the obtained PSNR value of the image is 31.68 while denoising it.

Performance analysis of pseudo 4-phase dual-rail asynchronous protocol

This article presents the performance analysis of novel pseudo 4-phase dual-rail protocol with self-reset and multiple-reset logic for high speed asynchronous applications. The self-reset logic eliminates the need for separate empty phase and hence reduces the number of transitions at the input and the output. The multiple-reset logic reduces the reset phase and hence increases the throughput. The performance of the pseudo 4-phase dual-rail protocol is compared with the existing 4-phase dual-rail protocol by implementing 8-bit and 16-bit asynchronously pipelined carry look ahead adders (CLA) in 0.35 µm technology. The time period decreases up to 32.58% and 35.93% respectively, the reset phase reduces up to 66.39% and 76.18%, respectively, and the operating frequency increases up to 48.4% and 56.2%, respectively, for 8- and 16-bit CLA adders with the pseudo 4-phase dual-rail protocol compared to the conventional 4-phase dual-rail protocol at the cost of increase in area of 8.8% and 3.3%, respectively. The delay-power product in ns-mW of the 8- and 16-bit CLAs is reduced at the maximum of 11.29% and 23.74%, respectively, with the pseudo 4-phase dual-rail protocol compared to the conventional 4-phase dual-rail protocol. The pseudo 4-phase dual-rail protocol is suitable for interfacing with synchronous environments.

Design and Implementation of Online Clock Skew Scheme-based Asynchronous Wave-pipelined Distributed Arithmetic Filters on FPGA

Abstract In this paper, Design and implementation of asynchronous wave-pipelined (WP) Distributed Arithmetic (DA) Alters on FPGA using online clock skew scheme is proposed. DA Alters of 8-taps, 16-taps, and 32-taps are implemented on an FPGA using non-pipelining (NP), pipelining, and WP schemes and compared with that of self-tuned scheme reported in the literature. The WP DA filters operate 1.4 to 1.53 times faster than NP DA filters. The delay-power products of the WP DA filters of 8-taps, 16-taps, and 32-taps using Online Clock Skew Scheme are less by 51.24%, 29.6%, and 3.78%, respectively, compared to those using Self-tuned Scheme.

Transient current sensing based completion detection with event separation logic for high speed asynchronous pipelines

This paper proposes a novel power supply transient current sensing based completion detector for single rail asynchronous systems to achieve high throughput compared to systems using speculative delay. This paper also proposes a new event separator logic for separating data tokens, in situations where the current sensor is idle due to consecutively same inputs. This type of logic is indispensable for asynchronous systems that use current sensing for completion detection. In order to prove the efficacy of the proposed CSCD, an asynchronous 8-bit Add-Compare-Select unit (ACSU) is simulated through HSPICE in 0.18µm CMOS process operating at 1V with the proposed CSCD with event separator over MOUSETRAP and also with matched delay over MOUSETRAP. The throughput of the proposed CSCD is 2.2Gsps which is 37.5% higher than that of the matched delay whose throughput is 1.6Gsps.

Asynchronous pipelined MB-OFDM UWB transceiver on FPGA

The key requirement of 200Mbps MB-OFDM UWB wireless system is that the OFDM block which is a 128 point FFT/IFFT processor has to operate at 528 MHz. The same way, a 64 state, rate-1/3 Viterbi decoder block is needed but this has to operate at 125MHz. Novel schemes are essential for achieving these speeds on FPGAs. In this paper, novel schemes are proposed to meet the challenges of FPGA based OFDM and Viterbi decoder blocks to implement MB-OFDM UWB transceiver. The advantages of asynchronous pipelining techniques are high speed, low power consumption, absence of clock-skew problem, etc., In this paper, as an initiative work, FPGA based MB-OFDM UWB transceiver using asynchronous pipelining technique with proposed schemes is presented. Bundled-data protocol with four-phase is used for asynchronous implementation. The OFDM module is designed using Two-parallel data path Radix-24 SDF FFT/IFFT with modified structure to obtain the required operating frequency of 528 MHz. A two-stage radix-4 Viterbi decoder with 2-pointer algorithm is proposed to reduce the memory requirement and latency of the previous implemented 3-pointer algorithm. LPM modules from ALTERA is also used to achieve the high speed requirement of MB-OFDM UWB system. The proposed asynchronously pipelined MB-OFDM UWB transceiver digital backend modules has been tested on ALTERA STRATIX III EP3SE110F780C2 FPGA by forming Digital loop back and the results are compliance to the ECMA 368 standard. To the best of our knowledge, the proposed work is first of its kind.