Maâmar El-Amine Hamri

A Generalized Discrete Event System (G-DEVS) Flattened Simulation Structure: Application to High-Level Architecture (HLA) Compliant Simulation of Workflow

The objective of the paper is to specify a new flattened Generalized Discrete Event System simulation engine structure and the Workflow modeling and simulation environment embedding it. We express first the new flattened simulation structure and give the corresponding transformation functions. We analyze performance tests conducted on this new simulation structure to measure its efficiency. Then, having selected the essential concepts in the elaboration of the Workflow, we present a language of description to define the Workflow processes. Finally, we define a distributed Workflow Reference Model that interfaces components of the Workflow with respect to the High-Level Architecture standard. Today enterprises can take advantage of this platform in the context of networking where interoperability, flexibility, and efficiency are challenging concepts.

Min–Max-DEVS modeling and simulation

Abstract The representation of timing, a key element in modeling hardware behavior, is realized in hardware description languages including ADLIB-SABLE, Verilog, and VHDL, through delay constructs. The use of delays in the literature may be organized into four classes. Under the first category, the mean values are utilized as precise delay elements in the simulators. VHDL adopts this view to characterize transport delays, where a single value is utilized, rise and fall delays, and inertial delays. In describing the lifetime of a state, also termed time advance function, DEVS proposes to use precise delay elements. Under the second category, termed min–max delay, a delay is represented through an interval, implying that the value of the delay is not known precisely and that any of the values in the interval represents a possible value for the actual delay. In the third category, a delay is expressed in the form of a stochastic distribution. The use of fuzzy models of delays constitutes the fourth category. In the real world, however, precise values for delays are very difficult, if not impossible, to obtain with certainty. The reasons include variations in the manufacturing process, temperature, voltage, and other environmental parameters. Consequently, simulations that employ precise delay values are susceptible to inaccurate results. This paper proposes an extension to the classical DEVS by introducing min–max delays for use in both internal and external transition functions. In the augmented formalism, termed Min–Max-DEVS, the state of a hardware model may, in some time interval, become unknown and is represented by the symbol, ϕ . The occurrence of ϕ implies greater accuracy of the results, not lack of information. Min–Max-DEVS offers a unique advantage, namely, the execution of a single simulation pass utilizing min–max delays is equivalent to multiple simulation passes, each corresponding to a set of precise delay values selected from the interval. This, in turn, poses a key challenge – efficient execution of the Min–Max-DEVS simulator.

Automatic generation of object-oriented code from DEVS graphical specifications

The paper presents an approach to automatically generate object-oriented code from DEVS graphical model specification. Afterward the generated DEVS code is given to the LSIS DME DEVS simulator to execute the corresponding behavior. This research is driven by the idea that the user of M&S, even not computer scientist and/or beginner in formal modeling like DEVS can increase his trust in the models he creates and the simulation results he is able to obtain due to the fact he is directly involved at the modeling stage and not anymore interfaced with an intermediate actor (modeler or programmer expert) that would interpret user requirements in the modeling and simulation activities. Using the proposed tool with its user friendly framework and appropriate graphical items, the user is capable to skip learning installation set up and user manual to rapidly develop his own DEVS models, to carry out simulations and to analyze them.

Complementarity between simulation and formal verification transformation of PROMELA models into FDDEVS models: Application to a case study

Discrete Event system Specification (DEVS) is a simple comprehensive way to describe complex discrete-event systems in a hierarchical way. Few years ago, Finite and Deterministic DEVS (FDDEVS) was introduced to support verification analysis of a subclass of DEVS problems, in the same way as formal methods. This paper presents guidelines to transform behavioral models used in formal methods like critical sections, especially described in PROMELA in this case, into FDDEVS models, and shows the benefits of such a transformation.

A Method for Improving the Verification and Validation of Systems by the Combined Use of Simulation and Formal Methods

Verification and Validation (V&V) of Systems is an important process in the development of systems, in order to ensure that they are reliable and operational. Among methods of V&V, there are two that seem to be opposite to each other: simulation, which is empirical, and formal verification, which is comprehensive. Moreover, simulation and formal verification propose many different formalisms, increasing the gap between them. But, jointly used, these two powerful tools allow making a more efficient verification, increasing the confidence we can put in the verified systems. The main problem is how we can combine their use and how we can reduce the gap created by the nature of both of them. This paper presents guidelines and a general approach in order to use simulation, and especially discrete-event simulation, on a model specified in a verifiable formal language.

Generalized Discrete Event Specifications of logic gates

In this paper, it is shown how the Generalized Discrete Event Specification paradigm can be advantageously used for logic gate modeling and simulation. The proposed approach is based on the use of piecewise-linear approximations for the representations of logic gates. It is noticed that the modeling part is independent from the simulation one.

Discrete event design patterns.

In this paper we highlight techniques from software engineering to design and code the behaviors of object. After a review of behavioral design patterns, we propose the state event design pattern to design basic behaviors described with state machines. In this pattern we objectify events in addition to states. Then, we generalize this pattern to DEVS behaviors. Thus, the DEVS designers may take profit from this technique to design simulations.

Why we should use Min Max DEVS for modeling and simulation of digital circuits

The delay is a very important element in modeling hardware behavior, and is realized in many hardware description languages such as ADLIB-SABLE, Verilog, and VHDL. The state of the art on hardware delay identifies four classes. In the first class, mean values are used as a precise delay element in the simulation; we found it in VHDL (VHSIC (very high speed integrated circuit) Hardware Description Language), where a single value is utilized to characterize the transport delay. In the second class, the delay is represented by an interval min max, meaning that the delay value is precisely unknown and every value in the interval can represent a possible value for the actual delay. In the third class, a delay is expressed in the form of a stochastic distribution. Fuzzy models of delay constitute the last class. In reality, it is very difficult, if not impossible, to obtain a precise value of the delay; there are many reasons for that: temperature, voltage, variation in the manufacturing process, and other environment parameters. The Min Max DEVS formalism allows an efficient design of the min max delay by proposing a definition of the lifetime function based on time interval. Moreover, its simulation semantics allows the simulation of Min Max DEVS models with only one replication, allowing us to conclude whether the min max delay is too large or exact simulations cannot be obtained. In this paper, we propose to highlight the Min Max DEVS formalism through examples from digital circuits, after having recalled its basic definitions and its simulation semantics. Then, we compare the simulation results obtained with those provided by the well-known tool in the field of digital circuits, Verilog, using the same examples.

DEv-PROMELA: an extension of PROMELA for the modelling, simulation and verification of discrete-event systems

PROMELA is a well-known formalism for the modelling and the verification of concurrent systems. PROMELA deals with high-level specifications. As a result, PROMELA models are expressed in a high-level abstraction which does not consider explicit representation of time or events for example. But, the efficiency of the processes of verification and validation relies on the accuracy of the models. That is why we propose, in this paper, work to develop a new extension of PROMELA for the modelling of discrete-event systems. The verification of these models is then done by combining formal verification and simulation-based verification using SPIN and the tool DEv-PROMELA Studio, or using any existing DEVS simulators.

Modeling and Simulation of Logic Gates using DEVS

Discrete event simulation becomes popular more and more and was applied successfully in many fields: medicine, robotics, etc. One of this field is digital circuits for which boolean logics is the basis of computation by designing logic gates. However such a paradigm does not consider the time basis. Consequently, the boolean logic paradigm can not design and simulate delays of circuits and stamped explicitly computations. In this paper, we propose to combine the boolean logic paradigm and Discrete EVent system Specification (DEVS) formalism for modeling and simulation logic gates. Using this approach, we are able to design complex network of logic gates by reusing and coupling basic ones and to analyze behavior through time.