Madhu Mutyam

Array-rewriting P systems

We consider array languages (sets of picturesconsisting of symbols placed in the lattice points of the 2D grid) and thepossibility to handle them with P systems. After proving binary normal formsfor array matrix grammars (which, even in the case when no appearance checking isused, are known to generate the array languages of arbitrary array grammars), weprove that the P systems with context-free rules (with three membranes and no control on the communication or the use of rules) are computationally universal, able togenerate all computable array languages. Some open problems are also formulated.

A bus encoding technique for power and cross-talk minimization

Considerable research has been done in the area of bus-encoding techniques, for either power minimization or cross-talk elimination in system-level buses, but not both together. We propose No Adjacent Transition (NAT) coding scheme, a bus encoding technique that simultaneously reduces power consumption and eliminates cross-talk. NAT-encoding and decoding algorithms are proposed and an analytical study of power dissipation is presented.

Preventing crosstalk delay using Fibonacci representation

As the CMOS technology scaled down to deep sub-micron level, the crosstalk effects due to the coupling capacitance between interconnection lines has become one of the main performance limiting factors. Several methods such as those based on routing strategies, skewing the timing of signals on adjacent wires, interleaving mutually exclusive buses, precharging the bus, and bus encoding technique, have been proposed to eliminate/reduce the crosstalk delay. In this work, we propose a bus encoding technique using a variant of binary Fibonacci representation to prevent crosstalk delay and give a recursive procedure to generate crosstalk delay free binary Fibonacci codewords. We show that m-bit crosstalk delay free binary Fibonacci codewords are used to encode /spl lfloor/log/sub 2/(F/sub m+2/)/spl rfloor/-bit bus, where F/sub m+2/ is the (m+2)/sup th/ Fibonacci number. So, a 32-bit bus can be encoded using 46-bit crosstalk delay free binary Fibonacci codewords.

P Systems with Membrane Creation: Universality and Efficiency

P systems, introduced by Gh. Paun form a new class of distributed computing model. Several variants of P systems were already shown to be computationally universal. In this paper, we propose a new variant of P systems, P systems with membrane creation, in which some objects are productive and create membranes. This new variant of P systems is capable of solving the Hamiltonian Path Problem in linear time. We show that P systems with membrane creation are computationally complete.

Process-Variation-Aware Adaptive Cache Architecture and Management

Fabricating circuits that employ ever-smaller transistors leads to dramatic variations in critical process parameters. This in turn results in large variations in execution/access latencies of different hardware components. This situation is even more severe for memory components due to minimum-sized transistors used in their design. Current design methodologies that are tuned for the worst case scenarios are becoming increasingly pessimistic from the performance angle, and thus, may not be a viable option at all for future designs. This paper makes two contributions targeting on-chip data caches. First, it presents an adaptive cache management policy based on nonuniform cache access. Second, it proposes a latency compensation approach that employs several circuit-level techniques to change the access latency of select cache lines based on the criticalities of the load instructions that access them. Our experiments reveal that both these techniques can recover significant amount of the lost performance due to worst case designs.

DeBAR: deflection based adaptive router with minimal buffering

Energy efficiency of the underlying communication framework plays a major role in the performance of multicore systems. NoCs with buffer-less routing are gaining popularity due to simplicity in the router design, low power consumption, and load balancing capacity. With minimal number of buffers, deflection routers evenly distribute the traffic across links. In this paper, we propose an adaptive deflection router, DeBAR, that uses a minimal set of central buffers to accommodate a fraction of mis-routed flits. DeBAR incorporates a hybrid flit ejection mechanism that gives the effect of dual ejection with a single ejection port, an innovative adaptive routing algorithm, and a selective flit buffering based on flit marking. Our proposed router design reduces the average flit latency and the deflection rate, and improves the throughput with respect to the existing minimally buffered deflection routers without any change in the critical path.

Fibonacci Codes for Crosstalk Avoidance

Propagation delay across long on-chip buses is significant when adjacent wires are transitioning in opposite direction (i.e., crosstalk transitions) as compared to transitioning in the same direction. By exploiting Fibonacci number system, we propose a family of Fibonacci coding techniques for crosstalk avoidance, relate them to some of the existing crosstalk avoidance techniques, and show how the encoding logic of one technique can be modified to generate codewords of the other technique.

Minimally buffered single-cycle deflection router

With the drift from computation centric designs to communication centric designs in the Chip Multi Processor (CMP) era, the interconnect fabric is gaining more importance. An efficient NoC in terms of power, area and average flit latency has a huge impact on the overall performance of a CMP. In the current work, we propose MinBSD - a minimally buffered, single cycle, deflection router. It incorporates different operations (Injection, Ejection, Preemption, Re-injection) in a single module to handle the traffic effectively and ensures smooth flow of flits through router pipeline. It performs overlapped execution of independent operations. These factors not only make MinBSD to operate in a single cycle but also to reduce the critical path latency resulting in a faster interconnect network. Experimental results show that MinBSD reduces the average flit latency on real work loads, reduces die area and power consumption when compared to the existing state-of-the-art minimally buffered deflection routers.

Block remap with turnoff: a variation-tolerant cache design technique

With reducing feature size, the effects of process variations are becoming more and more predominant. Memory components such as on-chip caches are more susceptible to such variations because of high density and small sized transistors present in them. Process variations can result in high access latency and leakage energy dissipation. This may lead to a functionally correct chip being rejected, resulting in reduced chip yield. In this paper, by considering a process variation affected on-chip data cache, we first analyze performance loss due to worst-case design techniques such as accessing the entire cache with the worst-case access latency or turning off the process variation affected cache blocks, and show that the worst-case design techniques result in significant performance loss and/or high leakage energy. Then by exploiting the fact that not all applications require full associativity at set-level, we propose a variation-tolerant design technique, namely, block remap with turnoff (BRT), to minimize performance loss and leakage energy consumption. In BRT technique we selectively turnoff few blocks after rearranging them in such a way that all sets get almost equal number of process variation affected blocks. By turning off process variation affected blocks of a set, leakage energy can be minimized and the set can be accessed with low latency at the cost of reduced set associativity. We validate our technique by running SPEC2000 CPU benchmark-suite on Simplescalar simulator and show that our technique significantly reduces the performance loss and leakage energy consumption due to process variations.

Word-interleaved cache: an energy efficient data cache architecture

We propose a novel energy-efficient data cache architecture, namely, word-interleaved (WI) cache. In theWI cache, a cache block is distributed uniformly among the different cache ways and each line of a cache way holds some words of the block. This distribution provides an opportunity to activate/deactivate the cache ways based on the requested addresss offset, thus minimizing the overall cache access energy. For a 4-way set associative cache of size 16KB and blocksize 32B, the proposed technique accomplishes dynamic energy savings of 54.2% without considering fast hits and 62.3% when fast hits are considered, with small performance degradation and negligible area overhead.