Magdy A. Bayoumi

A VLSI array for computing the DFT based on RNS

The Discrete Fourier Transform (DFT) has been adopted in a wide spectrum of Digital Signal Processing (DSP) applications due to the advances in VLSI technology, One dimensional systolic arrays are employed to implement the DFT algorithms where N DFT points can be computed in O(N) time using O(N) area. Residue Number System (RNS) is used to achieve parallelism on the mathematical level, as the arithmetic operations are performed independently for each modulus. Modularity has been realized on both functional and layout levels. Two types of arrays are described. The first array offers higher speed performance, while the second requires less area and is more general. The proposed structures are based on bit parallel processing and lend themselves to pipelining.

Models for VLSI implementation of residue number system arithmetic modules

This paper discusses the implementation of RNS arithmetic modules using VLSI technology. The modules are based on the interconnection of read-only memory look-up tables. The paper first outlines a memory model for a single look-up table which allows the selection of the most efficient layout for memories which do not have power of 2 dimensions. The paper then discusses various examples of interconnected memory modules with associated optimizing layout algorithms. Finally, an example is given of the application of one of the modules to a large prime modulus multiplier.

An area-time efficient NMOS adder

A model of computation for VLSI systems has been developed based on the Mead and Conway approach. This model accommodates the fan-out dependency in NMOS technology. Based on this model, a method for producing area-time efficient carry lookahead adders in NMOS has been developed. This method coordinates between the structural level (cells and interconnections) and the physical layout level (size of individual transistor). The proposed procedure exhibits modularity and regularity. Finally, an example of designing a 4-bit adder is given.

An efficient VLSI adder for DSP architectures based on RNS

The implementation of Residue Number System (RNS) architectures using the VLSI technology is discussed. An example of implementing an RNS adder is presented in this paper. Two approaches; the look-up table and the binary adder, have been analyzed in the scope of VLSI criteria where the performance measures are area and time. Two models have been developed, they are flexible, support any modulus, and they provide custom design capabilities. Within the context of this paper, it has been found that the look-up table approach is superior in both area and time up to 5 bits, while the binary adder approach offers better performance for larger moduli.

Testing of a NORA CMOS serial-parallel multiplier

The NORA-CMOS (no-race complementary metal-oxide-silicon) serial-parallel multiplier presented here is testable. Error detection is achieved at two levels: online functional testing and offline structural testing. Functional testing uses low-cost residue codes to detect errors at the overall level. Modulus is adopted as the check base. For structural testing, a NORA CMOS circuit error detection technique proposed based on the structure, properties, and operations of NORA CMOS is used. The proposed technique can detect output stuck-at, stuck-open, and stuck-on faults. Such a two-level testing strategy reduces test time and chip area overhead, identifies faulty locations, and has the ability to detect both transient and permanent faults. >

Parallel implementation of a cut and paste maze routing algorithm

Wire routing is a compute bound phase in the design of VLSI circuits. Some of the software solutions to this problem entail divide and conquer methods, such as hierarchical routing, in order to reduce its time complexity. Hardware accelerators have been employed to achieve further increase in the speed of this process. Implementation aspects of a reduced array architecture (RAA) for hardware acceleration of the cut and paste hierarchical routing algorithm are detailed. Several macros are defined to implement the algorithm in hardware. The architecture is implemented in double-metal 2-/spl mu/ CMOS technology.<<ETX>>

A VLSI implementation of finite impulse response digital filters using residue number systems

An array architecture is presented for implementing a finite impulse response (FIR) digital filter in a residue number system (RNS). A FIR filter requires only the high speed residue operations, i.e. addition and multiplication. VLSI is used as a fabrication medium to support the modular implementation. A general computation element is proposed as a building block unit. It is a multi look-up table module whose function is determined by the programmed contents of its associated tables. The proposed array is based on the systolic concept which provides high throughput and simplicity offered by identical processing elements, all operating in parallel on data synchronously flowing through the structure. The proposed architecture lends itself to the pipelining systems. It offers most efficient performance for continuous input data stream applications. An example of implementing a 24th-order filter is also given. The performance measures (area and time) of this filter are analyzed based on a developed memory model.

A systolic (VLSI) array using RNS for digital signal processing applications

A high speed one-dimensional systolic array is proposed for implementing finite impulse response (FIR) digital filters.The structure is completely pipelined, that is, the throughput rate (bits/sec.) is independent of the filter length.Residue Number System (RNS) is used for implementing the mathematical operations.RNS has a parallel nature where the arithmetic operations are performed independently for each modulus which enhances the system speed.VLSI is used as a fabrication medium which supports the modular implementation.The building block unit is a multi-look-up table module which has two possible configurations.The area-time complexity of an FIR structure is analyzed based on an RNS computational model.

The area-time complexity of a VLSI digital filter using residue number systems

Abstract Combining the Residue Number System (RNS) as a computational tool and VLSI as a fabrication medium promises to provide modular and cost efficient implementation of many digital signal processing algorithms. In this paper, a one-dimensional systolic array is used as a system structure to implement a finite impulse response (FIR) filter based on RNS. The building block unit of this structure is a multi look-up table module having two possible configurations. For this architecture a complexity analysis has been evaluated in terms of area and time. This analysis is based on RNS computational model. The structure is completely pipelined; that is, the throughput rate (bits/sec) is independent of the filter order. The upper bound of the system cycle (Tcycle) is 0 (n/log n).

A VLSI implementation of an FFT/NTT computational unit

The coupling of Residue Number System (RNS) with the recent advances in VLSI technology leads to an efficient implementation of many digital signal processing algorithms. This paper discusses modularity in implementing RNS systems, as modularity is considered an important criterion for VLSI design. An NTT/FFT computational unit is implemented using two multi-look-up table modules as building block units. The layout can be optimized using a look-up table layout procedure which supports the custom design approach. The modularity has been achieved on both functional and layout levels where the interconnection area is minimum.