Mahmoud Fawzy Wagdy

Determining ADC effective number of bits via histogram testing

A new application for one of the widely known A/D converter (ADC) dynamic testing methods, namely the histogram method, is discussed. After computing the transition voltages of the ADC transfer characteristics, the effective number of bits is computed. Simulation shows that this method more accurately characterizes the ADC used for arbitrary input signals, compared to the fast Fourier transform (FFT) and sine-fit methods which characterize the ADC in the light of an input sinusoid. The technique outperforms sinewave fitting as it gives more accurate results, while avoiding convergence problems of the iterative curve fitting algorithm. The FFT method was verified to be the least accurate. Simulation indications that the histogram method is better than the sine-fit method are presented. >

Linearizing average transfer characteristics of ideal ADC's via analog and digital dither

This paper is a continuation to the previous work by M.F. Wagdy (see ibid., vol. 38, p. 850-855, Aug. 1989). It further investigates the effect of various dither forms, i.e., with different probability density functions (PDFs), on the average observed transfer characteristics of ideal A/D converters (ADCs). First the deviation of the ADC characteristics from the ideal straight line is evaluated for analog dither forms using the concept of nonlinearity spectra developed in the above work. Second, two cases of digital (discrete) dither are investigated, one with rectangular envelope and the other with triangular one. Effects of dither peak-to-peak values and number of PDF impulses are investigated. The paper provides a quantitative basis for replacing analog dither with the easier to implement digital dither. >

Effect of sampling jitter on some sine wave measurements

The effects of sampling jitter on the measurement of amplitude and phase of a sinusoidal signal have been investigated. The parameters are determined by the fast Fourier transform (FFT) algorithm, which processes the samples following data acquisition. Results are expressed in terms of the mean values and variances of the measured parameters. Computer simulation results, based on Gaussian jitter show the changes of amplitude and phase standard deviations versus the changes of jitter standard deviation and signal amplitude for different numbers of samples, N. It is shown that amplitude and phase standard deviations are inversely proportional to square root N, and proportional to sigma /sub R/, the standard deviation of phase noise (jitter). This dependence on sigma /sub R/ means proportionality to both signal frequency and time jitter standard deviation. >

More on jitter effects on sinewave measurements

The measurement of signal-to-noise ratio (SNR) based on uniform sampling is investigated and compared with the results of Y. Jenq (see ibid., vol.37, p.245-251, June 1988) based on non-uniform sampling. Simulation results are provided to confirm the theoretical work. The authors then investigate amplitude and phase measurements and present new formulae for its statistics, which are more accurate than in their previous work (see ibid., vol.39, p.86-89, Feb. 1990). The approach followed in this study is also suitable for investigating signal measurements in the presence of other noise forms, e.g. quantization. >

A Fast-Locking Digital Phase-Locked Loop

A conventional digital phase-locked loop (DPLL) is designed using (Baker et al., 2003) to operate at 1GHz using 0.18 mum CMOS technology; its lock time is 4.19 mus. By adding a coarse/fine tuning control unit composed of a digital-to-analog converter (DAC) and a counter as well as switching the currents of the charge pump, a fast-locking DPLL results, with a lock time of 1.02 mus, i.e. an improvement by a factor of 4. Simulations for both DPLLs verified the performance improvement due to using a fast-locking technique

Comparative ADC performance evaluation using a new emulation model for flash ADC architectures

This paper investigates various flash A/D converters (ADCs) using a new emulation model which mimics the gate-level architecture of a flash ADC with any number of bits, n. The model is used for studying the effects of noise and offset voltages at the comparator inputs on the ADC output deviation using a mean-square error criterion. The first ADC investigated is the full-flash one, which is compared with the successive-approximation ADC for the same n. Then, two-step flash ADCs (i.e. half-flash) are investigated, with and without an interstage gain. Finally, error correction is attempted in conjunction with the later half-flash type.

A novel SAR Fast-locking digital PLL: Behavioral modeling and simulations using VHDL-AMS

A novel successive-approximation fast-locking digital phase-locked loop (SAR DPLL) is presented and behaviorally modeled using VHDL-AMS. The DPLL operation includes two stages: (1) a novel coarse-tuning stage for frequency tracking which employs a successive-approximation algorithm similar to the one employed in SAR A/D converters (ADCs) and (2) a fine-tuning stage for phase tracking which is similar to conventional DPLLs. The coarse-tuning stage includes a frequency comparator, a successive-approximation register, a D/A converter (DAC), and control logic. Design considerations and implementation are presented in this paper. VHDL-AMS and Ansoft Simplorer are used to design and perform simulations. The fast-locking DPLL saves about 50% of the lock time as compared to its conventional DPLL counterpart.

Various calibration algorithms for self-calibration A/D converters

Error cancellation of capacitor arrays in self-calibrating, successive approximation A/D converters is discussed. The two known methods are based on iterative sequential computation of the correction voltages used during A/D conversion. The original method employs one calibration capacitor, whereas the modified method requires N calibration capacitors for the N-bit converter. An algorithm is presented for determining the correction voltages, based on two source voltages generated by precision D/A converters. This allows direct measurement with no need for long sequential computations. >

A Novel Flash Fast-Locking Digital PLL: VHDL-AMS and Matlab/Simulink Modeling and Simulations

A novel flash fast-locking digital phase-locked loop (DPLL) is presented and behaviorally modeled. The DPLL operation includes two stages: (1) a novel coarse-tuning stage for frequency tracking which employs a flash algorithm similar to the one employed in flash A/D converters (ADCs) and (2) a fine-tuning stage similar to conventional (classical) DPLLs. The coarse-tuning stage includes an array of frequency comparators, a priority encoder, a digital-to-analog converter (DAC), and control logic. Design considerations and implementations are presented in this paper. VHDL-AMS (Simplorer) and Matlab/Simulink are used to design and perform simulations. The fast-locking DPLL reduces the lock time by a factor of about 1.80 compared to its conventional DPLL counterpart.

A Wide-Band Digital Phase-Locked Looop

A high speed digital phase-locked loop (DPLL) is designed using 0.18..m CMOS process, using a 3.3V power supply. It operates in the frequency range 55MHz — 1.43GHz. A (PFD) phase frequency detector has a zero dead-zone by including delay elements in the Reset path. The current source used in the charge pump makes it insensitive to supply variations and provides ripple-free control voltage for the VCO (voltage controlled oscillator), which provides low jitter and no overshoot in locking transients. A high damping factor of 1.65 is used to keep the PLL stable. Simulation results using CADENCE tools are provided to verify the desired performance.