Mahmoud Meribout

A Multisensor Intelligent Device for Real-Time Multiphase Flow Metering in Oil Fields

In this paper, a new multiphase flow metering device for real-time measurement of oil, gas, and water flow rates is presented. It is composed of several electrical and acoustic sensors whose signals are digitalized and processed by a multilayer neural network. This latest uses the physical models of multiphase fluids to reduce the complexity of the parameter space while improving its accuracy. Furthermore, to overcome the uncertainties of the electrical sensors in the range of 40%-60% and above 90% water-cut (i.e., ranges where most of the multiphase flow meter fail), two rings of high- and low-frequency ultrasonic sensors are used for low and high gas fractions, respectively. The results of experiments that have been conducted in an in-house laboratory-scale multiphase flow loop show that real-time classification for up to 90% gas fraction can be achieved with less than 10% relative error.

Perception Sensor for a Mobile Robot

A perception sensor for a mobile robot based on a reconfigurable and flexible parallel architecture is developed. Low-level image processing is implemented by using reprogrammable FPGA technology, and high-level image processing is performed by a dedicated reconfigurable parallel architecture based on digital signal processor TMS320C40. Hierarchical LINDA permits user-friendly parallel programming and real-time application. To show that our perception system can adapt to any application, we undertake the parallelization of a 3D scene-reconstruction algorithm using a geometric method, to meet the application response time (10 Hz).

An Accurate Machine for Real-Time Two-Phase Flowmetering in a Laboratory-Scale Flow Loop

A new flow measurement system for real-time flow computation of a two-phase flow in an oil field is described. The system utilizes an array of ultrasound sensors together with capacitance and conductance sensors to accurately interpret the fluid composition in the whole water-cut range. The flow rate is determined using venturi and differential pressure techniques. A dedicated hierarchical neural network algorithm that relies on the various physical properties of the fluid was implemented and tested in a laboratory-scale flow loop. Experimental results demonstrated that real-time classification within a plusmn5% relative error in volumetric flow regardless of the flow regime or the fluid composition can be achieved. This is an improvement over traditional systems, where weak accuracy is usually obtained either within the 40%-60% water-cut range or in the case of a high water cut.

A Real-Time Image Segmentation on a Massively Parallel Architecture

The method described in this paper enables the two end points of a straight line to be obtained by a Modified Double Hough Transform (MDHT). It consists respectively of line detection, followed by segment extraction. The significance of this work is that the hardware implementation is based on the Content Addressable Memory (CAM) concept. Hence, during the first HT, voting is achieved for the every scan line of image, not every edge pixel. Therefore, all the steps which form the first HT: voting, thresholding and local maximum are achieved in a low constant time. The two end points of the line are extracted through the second HT. Here, a local neighbor parallel search is also achieved at the end of each scan line of the image not at every edge pixel. Therefore, the execution time is low since the neighboring range does not exceed a few lines. Experimental results are given to show the accuracy of our approach for use in high performance pattern recognition systems.

An acoustic system for providing the two-phase liquid profile in oil field storage tanks

The continuing need for in situ measurements of the emulsion layer between crude oil and water within oil field tanks has initiated experimental and theoretical investigations of candidate measurement methods. This paper describes a new low-cost and nonradioactive industrial field prototype device that provides, continuously and in real time, the vertical profile of the 2-phase liquid within oil field tank separators (i.e., percentage of water in oil at different heights of the tank, as well as the emulsion layer interfaces) using ultrasonic waves. The device, which has been installed in a vessel through an 8-in. flange, consists of a 1-D array of tens of ultrasonic transducers (28 transducers in this paper) that are activated in a time-multiplexed manner by an embedded transmitter fixed on the top of the tank. This latest version implements a feedforward neural network with back-propagation learning to determine the vertical water-cut distribution along the vessel. It also implements an expert-system-based algorithm to determine the lower and higher positions of the emulsion layer. The results obtained from the extensive experiments, which have been conducted under various conditions of temperature, indicate that the device can determine the profile of the 2-phase liquid within a relative error of plusmn 3%.

New design methodology with efficient prediction of quality metrics for logic level design towards dynamic reconfigurable logic

The importance of efficient area and timing estimation is well established in high level synthesis (HLS) since it allows more efficient exploration of the design space while providing HLS tools with the capability of predicting the effects of technology specific tools on the design space. Much of the previous work has focused on estimation techniques that use very simple cost models based solely on functional units (FUs). Those models are not accurate enough to allow effective design space exploration since the effects of interconnects can indeed dominate the final design cost. The situation becomes even worst when the design is targeted to dynamically reconfigurable logic (DRL) technologies since the multiplexer delay may contribute heavily on the overall delay. In addition, large number of configurable logic blocks could be used for communication rather than for implementing FUs. In this paper we Present a new HLS design flow, which performs an accurate estimation on area and timing for DRL circuits. It takes into account not only FUs area and delay, but also the interconnection and communication effects. We select our DRL LSI circuit [M. Meribout, M. Motomura, Method for compiling high level programs into hardware, Japanese Patent: JSP2000-313818, 2000; M. Motomura et al., An embedded DRAM-FPGA chip with instantaneous logic reconfiguration, in: Symposium on VLSI Circuits, July 1997, pp. 55-56] as our main concentration. We tested our method with several benchmarks and the results show that we receive good performance of the design, with area and timing estimated efficiently.

Design and implementation of a new non-radioactive remote oil tank monitoring system

In the oil industry, many applications require the measurement of more than one liquid level interface, often in challenging environments. In this paper, a new sonar technique has been developed for emulsion layer detection. A dedicated compact, low-cost, and programmable Multi-layer level measurement (MLLM) device has been designed and implemented. The advantages of the new method over the current methods include contactless distance measurement, higher accuracy, lower cost, user friendly, simpler setup, and using non-nuclear rays. Additionally, the use of sonar waves has the advantage over light-based methods of being insensitive to dusty and smoky environment and almost independent of the object material and surface. Preliminary experiments have been conducted on the device and evidence for the satisfactory performance is given.

Detection and removal of video defects using rational-based techniques

This paper presents a Rational and Vector Rational based interpolator methods for reconstruction of missing data in video sequences. The interpolation of missing data is important in many areas of image processing, including the restoration of degraded motion pictures, reconstruction of dropouts in digital video and automatic re-touching of old photographs. Here, a detection technique is investigated for localization of the defects, and then a spatial vector rational interpolator algorithm is proposed to, reconstruct the missing data. This algorithm exhibits desirable properties, such as, edge and details preservation and accurate chromaticity estimation. In such approach, color image pixels are considered as three-component vectors in the color space that is more appropriate for the human visual system. Therefore, the inherent correlation that exists between the different color components is not ignored. This leads to better image quality compared to that obtained by component-wise or marginal processing. The experimental results demonstrate the usefulness of the vector rational interpolator in an application involving the restoration of defects in video sequences. The resulting edges obtained using the proposed interpolator are free from blockiness and jaggedness. The complexity evaluation of the algorithm shows that the implementation of the algorithm on a dedicated IMAP-based parallel hardware architecture can lead to an execution time of 5.7 and 15.6 ms for (256×256) binary and color images, respectively.

On using a new dynamic reconfigurable logic (DRL) VLSI circuit for very high speed routing

Recent efforts to add new services to the Internet have increased the interest in designing flexible routers that are easy to extend and evolve. This paper describes a new hardware architecture based on dynamic reconfigurable logic (DRL) for high throughput networking applications. It mainly focuses on content-based router and on how to schedule efficiently its computation time. This scheduling task is difficult because of the various features of the underlying hardware such as multicontext, control-data path architecture and memory interface. Experimental results show improvements over most recent network processors as well as a better hardware synthesis methodology.

A new reconfigurable hardware architecture for high throughput networking applications and its design methodology

Recent efforts to add new services to the Internet have increased the interest in designing flexible routers that are easy to extend and evolve. This paper describes a new hardware architecture based on dynamic reconfigurable logic (DRL) for high throughput networking applications. It mainly focuses on the content-based router and on how to schedule efficiently its computation time. This scheduling task is difficult because of the various features of the underlying hardware such as multicontext, control-data path architecture and memory interface. Experimental results show some improvements over most recent network processors as well as a better hardware synthesis methodology.