Majid Jalalifar

A

This letter presents a divide-by-five injection-locked frequency divider (ILFD) using a near-threshold (NT) VCO. The input frequency is injected in the proposed ILFD by a VCO employing a noise-cancelling technique. Both the proposed ILFD and VCO are based on a single compact coil which consists of a distributed and center-tapped inductor for an enhanced ILFD locking range of 20.2 to 21.9 GHz without varactors. The proposed VCO and ILFD are fabricated in a 0.13 μm CMOS process and consume 0.3 and 0.55 mW, respectively, from a 0.45 V supply.

K

In this letter, a quadrature voltage-controlled oscillator (QVCO) using PMOS transistors to couple two VCO cores is presented. The power consumption is drastically reduced by using the bulk of the PMOS transistors to lower the transconductance of both differential pairs in the coupling network. The QVCO achieves a measured phase noise of -116.02 dBc/Hz at 1 MHz offset and a quadrature phase error of 0.48 ° with a center frequency of 3.5 GHz. The proposed QVCO consumes 230 μW from a 0.45 V supply voltage. The QVCO is implemented in a standard 0.13 μm CMOS process with core area of 0.315 mm2.

-Band Divide-by-Five Injection-Locked Frequency Divider Using a Near-Threshold VCO

This paper presents a four-level pulse amplitude modulation (4-PAM) memory I/O interface for 3D stacked DRAMs. 3D integration technology is a promising solution for higher bandwidth and less power consumption due to the shortened link distance. The proposed transceiver is designed for 3D interconnects. The proposed transmitter employs a current mode output driver which sends data through TSVs. The receiver side uses differential amplifiers to decode three voltage levels by comparing the PAM signal with three reference voltages. The proposed scheme is simulated in 40 nm CMOS technology at 1.0 V. We use a highly accurate 3D electromagnetic (EM) simulator such as HFSS for 3D TSV channels simulations. The proposed architecture reduces the power consumption compared with prior works. It also increases the data bandwidth to 6.4 Gb/s/pin. Energy efficiency of proposed 3D mobile PAM I/O memory interface is 1.7 pJ/bit/pin.

An Ultra-Low Power QVCO Using Current-Coupling and Bulk-Injection Techniques

A current-reused back-gate coupling quadrature voltage-controlled oscillator (QVCO) using transformer feedback for K- band frequency applications is presented. The coupling scheme used to couple the two VCOs is a back-gate technique which removes the need for any extra coupling components that would degrade the phase noise performance and increase the power consumption. Utilizing current-reuse topology, which is inherently immune to the phase noise degradation, eliminates the second harmonic term at the common-source node of the conventional QVCOs. Moreover, the transformer feedback structure allows the QVCO to operate at low supply voltage. The tuning range of the proposed QVCO is 23.65-24.85 GHz, making the device applicable for K- band frequency wireless transceivers. The QVCO achieves a phase noise of -119.4 dBc/Hz at 1 MHz offset with a center frequency of 24 GHz as well as consumes 3.86 mW from a 0.8 V supply voltage. The QVCO is implemented in a standard 0.13 μm CMOS process with core area of 0.29 mm2.

An energy-efficient mobile PAM memory interface for future 3D stacked mobile DRAMs

An ultra-low power spike detector has been developed for implantable neural recording microsystems. The proposed circuit amplifies neural spikes with a pre-amplifier with a gain of 25.5 dB and then signals are compared with a detection threshold in a 25 dB comparator circuit. The spike detector simulated in a 0.13 μm standard CMOS process consumes 56.5 μW while being biased from a 0.7 V power supply.

A Current-Reused Back-Gate Coupling QVCO Using Transformer Feedback Structure

A phase-locked loop (PLL) along with a linear phase interpolator that generates 64 phases with low jitter in a continuous lock range of 400 MHz–2.2 GHz for mobile memory interfaces is presented. To provide adaptive and precise phase interpolation (PI), a novel frequency tracking PI bias along with a wide-frequency range PLL and lock-detection control are employed. The PLL-based PI is fabricated in 65-nm CMOS and achieves a peak-to-peak and an RMS jitter of 14.8 ps and 2.16 ps, respectively. The measured DNL and INL of the proposed PI are 0.21 LSB and 0.43 LSB, respectively. The PLL-based PI consumes 8.1 mW at a 1.0-V supply.

An ultra-low power spike detector for implantable biomedical systems

A simultaneous and reconfigurable multi-level RF-interconnect (MRI) for global network-on-chip (NoC) communication is demonstrated. The proposed MRI interface consists of baseband (BB) and RF band transceivers. The BB transceiver uses multi-level signaling (MLS) to enhance communication bandwidth. The RF-band transceiver utilizes amplitude-shift keying (ASK) modulation to support simultaneous communication on a shared single-ended on-chip global interconnect. A phase-locked loop (PLL) is also designed to support the fully-synchronous NoC architecture. The MLS-based BB and ASK-based RF band carry 10Gb/s/pin and 4.4Gb/s/pin, respectively. The proposed system is fabricated in a 65nm CMOS process and achieves an energy/b/pin/mm of 230fJ/b/pin/mm.

A Wide-Range Low-Power PLL-Based PI Multiphase Generator Using an Adaptive Frequency Tracking Technique

A near-threshold amplitude shift keying (NT-ASK) transmitter for biomedical implants is presented in this paper. The ASK transmitter supports a 100-Mb/s baseband data rate with a carrier frequency of 2.4 GHz. The design incorporates an LC voltage-controlled oscillator (VCO), ASK modulator, and a class-E power amplifier. The carrier is generated by a low phase noise LC-VCO, and then directly modulated by an NT-ASK modulator. The modulated signal is amplified by a class-E power amplifier and transmitted through an inductive coil. The transmitter achieves a total power consumption of 1.65 mW at 0.5 V, an energy efficiency of 16.5 pJ/b, and a phase noise of -115.7 dBc/Hz at 1-MHz offset at a center frequency of 2.4 GHz. The output power level of the transmitter is -14 dBm. The ASK transmitter is implemented in a standard 0.13-μm CMOS process with a core area of 0.63 mm2.

A 14.4Gb/s/pin 230fJ/b/pin/mm multi-level RF-interconnect for global network-on-chip communication

A three-stage low noise amplifier (LNA) using dual positive feedback is presented in this paper. In order to increase voltage gain and forward gain, two positive feedbacks are employed in the LNA circuit. Moreover, the LNA transistors operate at a moderate inversion region, so it is suitable to use in an ultra-low voltage receiver. The proposed LNA is simulated in 0.13μm CMOS technology. The results show that the LNA achieves a minimum noise figure of 3.28dB, a 28dB voltage gain, and a 15.8dB forward gain at 7.1GHz. The LNA consumes 0.92mW from a 0.5V power supply.