Makoto Nagata

Physical design guides for substrate noise reduction in CMOS digital circuits

Substrate noise injection in large-scale CMOS logic integrated circuits is quantitatively evaluated by 100-/spl mu/V 100-ps resolution substrate noise measurements of controlled substrate noises by a transition-controllable noise source and practical substrate noises under CMOS logic operations. The noise injection is dominated by leaks of supply/return bounce into the substrate, and the noise intensity is determined by logic transition activity, according to experimental observations. A time-series divided parasitic capacitance model is derived as an efficient estimator of the supply current for simulating the substrate noise injection and can reproduce the measured substrate noise waveforms. The efficacy of physical noise reduction techniques at the layout and circuit levels is quantified and limitations are discussed in conjunction with the noise injection mechanisms. The reduced supply bounce CMOS circuit is proposed as a universal noise reduction technique, and more than 90% noise reduction to conventional CMOS is demonstrated.

Measurements and analyses of substrate noise waveform in mixed-signal IC environment

A transition-controllable noise source is developed in a 0.1-/spl mu/m P-substrate N-well CMOS technology. This noise source can generate substrate noises with controlled transitions in size, interstage delay and direction for experimental studies on substrate noise properties in a mixed-signal integrated circuit environment. Substrate noise measurements of 100 ps, 100-/spl mu/s resolution are performed by indirect sensing that uses the threshold voltage shift in a latch comparator and by direct probing that uses a PMOS source follower. Measured waveforms indicate that peaks reflecting logic transition frequencies have a time constant that is more than ten times larger than the switching time. Analyses with equivalent circuits confirm that charge transfer between the entire parasitic capacitance in digital circuits and an external supply through parasitic impedance to supply/return paths dominates the process, and the resultant return bounce appears as the substrate noise.

Reduced substrate noise digital design for improving embedded analog performance

Substrate crosstalk reduction is necessary for reliable high performance mixed signal LSI design. The paper demonstrates more than 67% reduction as a consequence of supply bounce suppression.

A PWM signal processing core circuit based on a switched current integration technique

A highly functional circuit for pulse width modulation (PWM) signal processing is proposed as a core of the A-D merged circuit architecture for time-domain information processing. The core circuit employs a switched-current integration technique as its computing architecture and functions as a linear arithmetic operator, a memory, and also a delaying device of PWM signals. A 0.8-/spl mu/m CMOS test chip includes 110 transistors plus two capacitors and performs parallel additions and multiplications at the accuracy of 1.2 ns. A cumulative property of the technique allows the circuit to serve as a low-power accumulator that consumes 23% of the energy of the full digital 7-b accumulator. A PWM multiply-accumulate unit and a nonlinear operation unit are also proposed to extend functionality of the circuit. Since the PWM signal carries multibit data in a binary amplitude pulse, these circuits can be favorably applicable to low-voltage and low-power designs in the deep submicrometer era.

Substrate Noise Simulation Techniques for Analog-Digital Mixed LSI Design

Crosstalk from digital to analog circuits can be causative of operation fails in analog-digital mixed LSIs. This paper describes modeling techniques and simulation strategies of the substrate coupling noise. A macroscopic substrate noise model that expresses the noise as a function of logic state transition frequencies among digital blocks is proposed. A simulation system based on the model is implemented in the mixed signal simulation environment, where performance degradation of the 2nd order ΔΣADC coupled to digital noise sources is clearly simulated. These results indicate that the proposed behavioral modeling approach allows practicable full chip substrate noise simulation measures.

Measurements and analyses of substrate noise waveform in mixed signal IC environment

A transition controllable noise source is developed in a 0.4 /spl mu/m CMOS, P-substrate N-well technology, for experimental studies on substrate noise properties in a mixed signal IC environment. The number of active logic elements, transition directions, and delays can be controlled. Measured substrate noise waveforms with 100 ps time resolution show that peaks in substrate voltage, reflecting logic transition frequencies, have a time constant a few times larger than the switching time. Analyses with equivalent circuits make it clear that this process results from charge transfer between parasitic capacitance of entire logic circuits and an external supply, through supply/return parasitic impedance.

A single-electron stochastic associative processing circuit robust to random background-charge effects and its structure using nanocrystal floating-gate transistors

A new single-electron circuit using the unique features of single-electron devices is proposed, based on a basic strategy and circuit architecture for achieving large-scale integration. A unit circuit consisting of a single-electron transistor and a capacitor operates as an exclusive-NOR gate by the Coulomb blockade effect, and its transient behaviour is stochastic due to electron-tunnelling events. Using this unit circuit, a stochastic associative processing circuit is proposed, based on a new information-processing principle where the association probability depends on the similarity between the input and reference data. This circuit can be constructed by using a silicon nanocrystal floating-gate structure in which dots are regularly arranged on a gate electrode of a MOSFET. The simulation results of a simple digit pattern association demonstrate the successful stochastic operation. The background-charge effects on the proposed circuit are analysed and simulated, and it is shown that the circuit is much more robust to such effects than the conventional single-electron logic circuits.

A minimum-distance search circuit using dual-line PWM signal processing and charge-packet counting techniques

This CMOS minimum distance search circuit (MDS) realizes pattern matching engines for multi-media and intelligent processing systems. The chip executes highly-parallel computation of Manhattan distances between an input vector and stored multiple reference vectors, and search of the minimum distance among them. Two novel circuit techniques are based on pulse width modulation (PWM) analog-digital merged circuits.

A concept of analog-digital merged circuit architecture for future VLSI's

This paper describes the new analog-digital merged circuit architecture which utilizes the pulse modulation signals. By reconsidering the information representing and processing principles, and the circuit operations governed by the physical law, the new circuit architecture is proposed to overcome the limitations of existent VLSI technologies. The proposed architecture utilizes the pulse width modulation (PWM) signal which has analog information in the time domain, and be constructed with the novel PWM circuits which carry out the multi-input arithmetic operations, the signal conversions and the data storage. It has a potential to exploit the high speed switching capability of deep sub-μm devices, and to reduce the number of devices and the power dissipation to one-tenth of those of the binary digital circuits. Therefore it will effectively implement the intelligent processing systems utilizing 0.5–0.2 μm scaled CMOS devices.

Modeling substrate noise generation in CMOS digital integrated circuits

A time-series divided parasitic capacitance model accurately simulates substrate noise generation of practical CMOS digital integrated circuits in the time domain. The simulation of a 0.25-/spl mu/m z80 microcontroller with 62.5-MHz clock frequency costs less than 10 sec per a clock cycle including the model generation. Simulated substrate noise compares well with 200-ps 100-/spl mu/V resolution measurements in wave-shapes validated for clock frequency up to 125 MHz and shows a peak-amplitude error of less than 2% against supply-voltage scaling from 2.5 V to 1.6 V.