Makoto Suzuki

3.3-V BiCMOS circuit techniques for 250-MHz RISC arithmetic modules

A quasi-complementary BiCMOS gate for low-voltage supply is applied to a 3.3V RISC data path. For a parallel RISC processor, the major issues are the construction of arithmetic modules in a small number of transistors and the shortening of the cycle time as well as the delay time. The feedbacked massive-input logic (FML) concept is proposed to meet these requirements. It reduces the number of transistors and the power within the framework of fully static logic 3-4 times. A low-voltage BiCMOS D-flip-flop is also conceived to allow the single-phase clocking scheme, which is favorable for high-frequency operation of RISCs. To demonstrate these circuit techniques, a 32-b ALU is designed and fabricated using 0.3- mu m BiCMOS to demonstrate 1.6 times performance leverage over CMOS at 3.3 V. >

A 7-ns/350-mW 64-kbit ECL-compatible RAM

A 7-ns 350-mW, 64-kbit ECL RAM was developed using 1.3-/spl mu/m high-performance bipolar-CMOS (Hi-BiCMOS) technology, in which a bipolar transistor of 7-GHz cutoff frequency is fabricated together with 1.3-/spl mu/m CMOS. A variable-impedance data-line load, a common data-line equalizing circuit, and a sense-amplifier selection technique together achieve a 7-ns access time. Gates combining bipolar and CMOS devices achieve a power dissipation of one-third that of conventional bipolar 64-kb ECL RAMs.

A current-mode column comparator circuit for high-speed, low-power on-chip cache-TAG memories

The authors describe a low-power comparator circuit which is especially useful for on-chip cache-TAG memories. A novel TAG memory comparator circuit scheme, called a current-mode column comparator (CMCC) scheme, is proposed, and the low-power nature of the CMCC without degraded accessing speed is described. An experimental 128-entry by 32-b TAG-memory test chip was fabricated using 0.5-μm BiCMOS technology, and a 3-ns address input to hit delay time was obtained. The power dissipation of the sense amplifiers was reduced by a factor of 10

Dye concentration dependence of spectral triplet in one-dimensional photonic crystal with cyanine dye J-aggregate in strong coupling regime

We report on the dye concentration dependence of nonlinear transmission properties of one-dimensional photonic crystal microcavities containing cyanine dye J-aggregates. Using femtosecond nonlinear transmission spectroscopy, we observed a transition from a polariton doublet state to a spectral triplet state over the whole tested concentration range, even at room temperature. In these samples, changes in the dye concentration affected the Rabi splitting energy in the linear transmission measurements; however, we found that changes in the concentration did not greatly affect the triplet formation.