Makoto Yasuda

A 55nm Ultra Low Leakage Deeply Depleted Channel technology optimized for energy minimization in subthreshold SRAM and logic

This paper presents an Ultra-Low Leakage (ULL) 55nm Deeply Depleted Channel (DDC) process technology for low power Internet of Things (IoT) applications. The DDC ULL devices provide 67% reduction in threshold (VT) variation due to Random Dopant Fluctuation (RDF). Circuit techniques such as subthreshold operation and reverse body biasing (RBB) are co-designed with the technology to maximize the energy/power saving. A test chip implements a 1Kb 6T SRAM, an FIR filter, and a 51-stage RO to showcase how the technology works with circuit techniques to minimize energy. The 6T SRAM array operates reliably down to 200mV with a reduced leakage power of 7nW (85% lower compared to non-DDC devices). The FIR filter consumes just 4.5pJ/cycle operating at 0.36V at 200 KHz.

Fully understanding the mechanism of misalignment-induced narrow-transistor failure and carefully evaluating the misalignment-tolerant SRAM-cell layout

We have successfully demonstrated a misalignment-tolerant SRAM cell, whose layout has been created from consideration of narrow-transistor failure through physical and electrical analyses. To evaluate an advantage of the layout, we have performed an intentionally misaligned experiment using a test structure with each SRAM block featuring a neighbor alignment-inspection mark. Moreover, utilizing the result of the experiment, we have created a manufacturing-friendly methodology of misalignment-limit determination.

Fully Understanding the Mechanism of Misalignment-Induced Narrow-Transistor Failure and Carefully Evaluating the Misalignment-Tolerant SRAM-Cell Layout

We have successfully demonstrated a misalignment-tolerant SRAM cell, whose layout has been created from consideration of narrow-transistor failure through physical and electrical analyses. To evaluate an advantage of the layout, we have performed an intentionally misaligned experiment using a test structure with each SRAM block featuring a neighbor alignment-inspection mark. Moreover, utilizing the result of the experiment, we have created a manufacturing-friendly methodology of misalignment-limit determination.