Man L. Mui | Researchain

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Archive | 2013

THRESHOLD VOLTAGE ADJUSTMENT FOR A SELECT GATE TRANSISTOR IN A STACKED NON-VOLATILE MEMORY DEVICE

Haibo Li; Xiying Costa; Masaaki Higashitani; Man L. Mui

Archive | 2008

Built in on-chip data scrambler for non-volatile memory

Jun Wan; Yupin K. Fong; Man L. Mui

international solid-state circuits conference | 2009

A 16 Gb 3-Bit Per Cell (X3) NAND Flash Memory on 56 nm Technology With 8 MB/s Write Rate

Yan Li; Seungpil Lee; Yupin Fong; Feng Pan; Tien-Chien Kuo; Jongmin Park; Tapan Samaddar; Hao Thai Nguyen; Man L. Mui; Khin Htoo; Teruhiko Kamei; Masaaki Higashitani; Emilio Yero; Gyuwan Kwon; Phil Kliza; Jun Wan; Tetsuya Kaneko; Hiroshi Maejima; Hitoshi Shiga; Makoto Hamada; Norihiro Fujita; Kazunori Kanebako; Eugene Tam; Anne Koh; Iris Lu; Calvin Chia-Hong Kuo; Trung Pham; Jonathan Huynh; Qui Nguyen; Hardwell Chibvongodze

Archive | 2008

Method for scrambling data in which scrambling data and scrambled data are stored in corresponding non-volatile memory locations

Jun Wan; Yupin K. Fong; Man L. Mui

Archive | 2013

Erase Operation For 3D Non-Volatile Memory With Controllable Gate-Induced Drain Leakage Current

Xiying Costa; Haibo Li; Masaaki Higashitani; Man L. Mui

Archive | 2014

Erase For 3D Non-Volatile Memory With Sequential Selection Of Word Lines

Xiying Costa; Seung Yu; Roy E. Scheuerlein; Haibo Li; Man L. Mui

Archive | 2014

Bit line current trip point modulation for reading nonvolatile storage elements

Man L. Mui; Teruhiko Kamei; Yingda Dong; Ken Oowada; Yosuke Kato; Fumitoshi Ito; Seungpil Lee

Archive | 2014

Soft Erase Operation For 3D Non-Volatile Memory With Selective Inhibiting Of Passed Bits

Xiying Costa; Haibo Li; Masaaki Higashitani; Man L. Mui

Archive | 2013

Compensation For Temperature Dependence Of Bit Line Resistance

Chia-lin Hsiung; Mohan Dunga; Man L. Mui; Masaaki Higashitani

Archive | 2014

Dynamic erase voltage step size selection for 3D non-volatile memory

Wendy Ou; Man L. Mui; Yingda Dong; Masaaki Higashitani

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