Manfred Horstmann

Multiple Stress Memorization In Advanced SOI CMOS Technologies

Two distinct stress memorization phenomena in advanced SOI CMOS are reported in this work. Both require a capping layer and anneal, but can be categorized as techniques 1) requiring an amorphized source/drain region and low temperature anneal, and 2) requiring a high temperature anneal, independent of the crystalline state of the Si. Both improve NMOS drive current, and the resulting improvements are additive to >27% NMOS IDSAT improvement. The first phenomenon is previously unreported. It has been identified to be localized in the source/drains, and yields more improvement with multiple offset implantation prior to capping and annealing.

Taking SOI substrates and low-k dielectrics into high-volume microprocessor production

SOI and low-k technologies are rapidly approaching production maturity. This paper highlights several challenges found when moving them from development to high-volume manufacturing. In overcoming these challenges in wafer processing and transistor development, we have achieved yield learning and performance enhancement rates equivalent to or better than conventional technologies.

Implementation and optimization of asymmetric transistors in advanced SOI CMOS technologies for high performance microprocessors

Sub-40 nm Lgate asymmetric halo and source/drain extension transistors have been integrated into leading-edge 65 nm and 45 nm PD-SOI CMOS technologies. With optimization, the asymmetric NMOS and PMOS saturation drive currents improve up to 12% and 10%, respectively, resulting in performance at 1.0 V and 100 nA/mum IOFF of NIDSAT=1354 muA/mum and PIDSAT=857 muA/mum. Product-level implementation of asymmetric transistors showed a speed benefit of 12%, at matched yield and improved reliability.

Advanced transistor structures for high performance microprocessors

Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40nm gate length (L/sub GATE/) PD SOI transistors into volume manufacturing for high-speed microprocessors. The key innovations developed for this transistor in order to overcome classical gate oxide and LGATE scaling are an unique differential triple spacer structure, stressed overlayer films inducing strain in the Silicon channel and optimized junctions. This transistor structure yields an outstanding ring oscillator speed with an unloaded inverter delay of 5.5ps. The found improvements are highly manufacturable and scaleable for future device technologies like FD SOI.

Review on Process-Induced Strain Techniques for Advanced Logic Technologies

We have extensively studied stress enhancing techniques to increase channel mobility starting at the 130 nm technology node and continued this towards the 45 nm node. Stressed overlayers and spacer materials, strained SOI substrates, embedded SiGe and SiC layers and their proximity effects, the impact of different silicides, stress memorization and compatibility with laser and flash anneals have been investigated. The integration of abovementioned techniques into a CMOS flow resulted in an outstanding pMOS and nMOS performance improvement, no reliability issues and no impact on short channel behavior.

Compensation of operation-related F MAX degradation by adaptive control of circuit operating voltage

The impact of HCI and NBTI on device DC, Ring Oscillator (RO) AC as well as on the degradation of product operating frequency (FMAX) has been extensively studied. We have developed a method, which allows the compensation of HCI/NBTI-related device and product performance degradation by adaptive control of operating voltage and power for the integrated circuit. Depending on the constraints applied to the product reliability and power, full or partial performance compensation is possible applying our new approach. The win in guard bands and thus a product classification advantage is demonstrated on one of our high-performance microprocessors.

Line Edge and Gate Interface Roughness Simulations of Advanced VLSI SOI-MOSFETs

The influence of line edge and gate interface roughness on SOI-MOSFET performance is studied by simulation. Both types of roughness were implemented in the device simulator SIMBA through the Fourier synthesis approach and the simulations were performed with the drift diffusion and the quantum drift diffusion models. Scaled transistors showed more sensitivity to rough interfaces with shallow junctions.

Process Integration Issues with Spike, Flash and Laser Anneal Implementation for 90 and 65 NM Technologies

With the need to reduce vertical and lateral device dimensions, submelt laser and flash anneal either with or without prior spike rapid thermal anneal (sRTA) has recently attracted attention. It combines improved active area activation with reduced gate poly depletion for a process that is essentially free of additional diffusion. This paper will focus on process integration issues during implementation into 90 and 65 nm SOI logic technologies: Transistor parameter fluctuation and pattern effects, power density limitations and the impact on the reliability of ultra-thin gate oxides, compatibility with new materials such as SiGe, transistor scaling and performance enhancement

Scalability of advanced partially depleted n-MOSFET devices on biaxial strained SOI substrates

Biaxial tensile strained substrates offer strong electron mobility enhancements resulting in large drive current gains. For short channel n-MOSFETs, however, these improvements diminish. Root causes for this performance degradation are investigated through experiments and simulations. Elastic stress relaxation arising from shallow trench isolation (STI) is found to be negligible for current state-of-the-art transistors. On the other hand, parasitic source/drain resistance seems to be responsible for the limitation of drain current gains in deeply scaled devices. This effect is even further aggravated by an increased parasitic source/drain resistance in sSOI devices compared to standard SOI.

Recent advances in stress and activation engineering for high-performance logic transistors

SOI technology is leading edge for high performance microprocessors. Performance per Watt is key and multiple core devices and their improved functionality are required to keep power comsumption low. AMD runs a unique transistor node to node progression model which devlivers at all times top notch performance from technology and lowers risk when moving to next technology generation. AMD gained leadership on strained Si and multi stressor integration. In a very mature state already DSL, SMT and SiGe. Besides stressors, advanced anneal is important to reduce diffusion and asymmetric device will help transistor performance. Reduction of parametric scattering is especially important for 45nm/32nm technology nodes. A special in-die measurement method has been developed to assess scattering in a thorough statistical way. Existing stressors like DSL, SMT, SiGe fully scale to 45nm pitches. HK/MG materials are the key for 32nm to keep GOX leakage under control and to allow gate scaling again.