Manh Anh Do

A novel CMOS low-noise amplifier design for 3.1- to 10.6-GHz ultra-wide-band wireless receivers

An ultra-wideband (UWB) 3.1- to 10.6-GHz low-noise amplifier (LNA) employing a common-gate stage for wideband input matching is presented in this paper. Designed in a commercial 0.18-mum 1.8-V standard RFCMOS technology, the proposed UWB LNA achieves fully on-chip circuit implementation, contributing to the realization of a single-chip CMOS UWB receiver. The proposed UWB LNA achieves 16.7plusmn0.8 dB power gain with a good input match (S11<-9 dB) over the 7500-MHz bandwidth (from 3.1 GHz to 10.6 GHz), and an average noise figure of 4.0 dB, while drawing 18.4-mA dc biasing current from the 1.8-V power supply. A gain control mechanism is also introduced for the first time in the proposed design by varying the biasing current of the gain stage without influencing the other figures of merit of the circuit so as to accommodate the UWB LNA in various UWB wireless transmission systems with different link budgets

A compact size coupling controllable filter with separate electric and magnetic coupling paths

This paper presents the characteristics of a miniaturized microstrip filter, which has two separate coupling paths: electric coupling path and magnetic coupling path between two resonators. Either magnetic coupling or electric coupling in two paths can be dominant in the total coupling coefficient of the inter-stage resonators with the similar configuration, but different positions of transmission zero points (ZPs). Based on the proposed filter topology, second- and fourth-order filters have been designed and fabricated for the first time. Advantages of using this type of filter are not only its low insertion loss and much more compact size, but also its controllable transmission ZPs.

Design and Optimization of the Extended True Single-Phase Clock-Based Prescaler

The power consumption and operating frequency of the extended true single-phase clock (E-TSPC)-based frequency divider is investigated. The short-circuit power and the switching power in the E-TSPC-based divider are calculated and simulated. A low-power divide-by-2/3 unit of a prescaler is proposed and implemented using a CMOS technology. Compared with the existing design, a 25% reduction of power consumption is achieved. A divide-by-8/9 dual-modulus prescaler implemented with this divide-by-2/3 unit using a 0.18-mum CMOS process is capable of operating up to 4 GHz with a low-power consumption. The prescaler is implemented in low-power high-resolution frequency dividers for wireless local area network applications

Design and Analysis of Ultra Low Power True Single Phase Clock CMOS 2/3 Prescaler

In this paper the power consumption and operating frequency of true single phase clock (TSPC) and extended true single phase clock (E-TSPC) frequency prescalers are investigated. Based on this study a new low power and improved speed TSPC 2/3 prescaler is proposed which is silicon verified. Compared with the existing TSPC architectures the proposed 2/3 prescaler is capable of operating up to 5 GHz and ideally, a 67% reduction of power consumption is achieved when compared under the same technology at supply voltage of 1.8 V. This extremely low power consumption is achieved by radically decreasing the sizes of transistors, reducing the number of switching stages and blocking the power supply to one of the D flip-flops (DFF) during Divide-by-2 operation. A divide-by-32/33 dual modulus prescaler implemented with this 2/3 prescaler using a chartered 0.18 ¿m CMOS technology is capable of operating up to 4.5 GHz with a power consumption of 1.4 mW.

Broad-Band Design Techniques for Transimpedance Amplifiers

In this paper, a novel bandwidth enhancement technique based on the combination of capacitive degeneration, broad-band matching network, and the regulated cascode (RGC) input stage is proposed and analyzed, which turns the transimpedance amplifier (TIA) design into a fifth-order low-pass filter with Butterworth response. This broad-band design methodology for TIAs is presented with an example implemented in CHRT 0.18-mum 1.8-V RF CMOS technology. Measurement data shows a -3-dB bandwidth of about 8 GHz with 0.25-pF photodiode capacitance. Comparing with the core RGC TIA without capacitive degeneration and broad-band matching network, this design achieves an overall bandwidth enhancement ratio of 3.6 with very small gain ripple. The transimpedance gain is 53 dBOmega with a group delay of 80plusmn20 ps. The chip consumes only 13.5-mW dc power and the measured average input-referred noise current spectral density is 18 pA/radicHz up to 10 GHz

A Subthreshold Low-Noise Amplifier Optimized for Ultra-Low-Power Applications in the ISM Band

The IEEE 802.15.4 standard relaxes the requirements on the receiver front-end making subthreshold operation a viable solution. The specification is discussed and guidelines are presented for a small area ultra-low-power design. A subthreshold biased low-noise amplifier (LNA) has been designed and fabricated for the 2.4-GHz IEEE 802.15.4 standard using a standard low-cost 0.18-mum RF CMOS process. The single-stage LNA saves on chip area by using only one inductor. The measured gain is more than 20 dB with an S11 of -19 dB while using 630 muA of dc current. The measured noise figure is 5.2 dB.

Design of a CMOS Broadband Transimpedance Amplifier With Active Feedback

In this paper, a novel current-mode transimpedance amplifier (TIA) exploiting the common gate input stage with common source active feedback has been realized in CHRT 0.18 ¿m -1.8 V RFCMOS technology. The proposed active feedback TIA input stage is able to achieve a low input impedance similar to that of the well-known regulated cascode (RGC) topology. The proposed TIA also employs series inductive peaking and capacitive degeneration techniques to enhance the bandwidth and the gain. The measured transimpedance gain is 54.6 dB¿ with a -3 dB bandwidth of about 7 GHz for a total input parasitic capacitance of 0.3 pF. The measured average input referred noise current spectral density is about 17.5 pA/¿{Hz} up to 7 GHz. The measured group delay is within 65 ± 10 ps over the bandwidth of interest. The chip consumes 18.6 mW DC power from a single 1.8 V supply. The mathematical analysis of the proposed TIA is presented together with a detailed noise analysis based on the van der Ziel MOSFET noise model. The effect of the induced gate noise in a broadband TIA is included.

9.3-10.4-GHz-band cross-coupled complementary oscillator with low phase-noise performance

A fully integrated 10-GHz-band voltage-controlled oscillator (VCO) has been designed and fabricated using commercial 0.18-/spl mu/m CMOS technology. The complementary cross-coupled differential topology is adopted in the design. The measured phase-noise is around -89 dBc/Hz at the offset frequency of 100 kHz from the center frequency of 9.83 GHz, the output frequency tuning range of the fabricated VCO is 1.1 GHz ranging from 9.3 to 10.4 GHz, and the power consumption of the core VCO circuit is 5.8 mW. The design is the first one that adopts the complementary cross-coupled circuit structure for 10-GHz-band oscillators, and whose performances of the VCO are the best ones for 10-GHz-band oscillators, compared with the 10-GHz-band CMOS oscillators reported earlier.

A Wideband Low Power Low-Noise Amplifier in CMOS Technology

A T-coil network can be implemented as a high order filter for bandwidth extension. This technique is incorporated into the design of the input matching and output peaking networks of a low-noise amplifier. The intrinsic capacitances within the transistors are exploited as a part of the wideband structure to extend the bandwidth. Using the proposed topology, a wideband low-noise amplifier with a bandwidth of 3-8 GHz, a maximum gain of 16.4 dB and noise figure of 2.9 dB (min) is achieved. The total power consumption of the wideband low-noise amplifier from the 1.8 V power supply is 3.9 mW. The prototype is fabricated in 0.18 ¿m CMOS technology.

A 1.8-V 2.4/5.15-GHz dual-band LCVCO in 0.18-/spl mu/m CMOS technology

A dual band, fully integrated, low phase-noise and low-power LC voltage-controlled oscillator (VCO) operating at the 2.4-GHz industrial scientific and medical band and 5.15-GHz unlicensed national information infrastructure band has been demonstrated in an 0.18-/spl mu/m CMOS process. At 1.8-V power supply voltage, the power dissipation is only 5.4mW for a 2.4-GHz band and 8mW for a 5.15-GHz band. The proposed VCO features phase-noise of -135dBc/Hz at 3-MHz offset frequency away from the carrier frequency of 2.74GHz and -126dBc/Hz at 3-MHz offset frequency away from 5.49GHz. The oscillator is tuned from 2.2 to 2.85GHz in the low band (2.4-GHz band) and from 4.4 to 5.7GHz in the high band (5.15-GHz band).