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Manish K. Shah

Sun Microsystems

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Archive | 2004

Handling duplicate cache misses in a multithreaded/multi-core processor

Jama I. Barreh; Manish K. Shah

Archive | 2004

Level 2 cache index hashing to avoid hot spots

Greg Grohoski; Manish K. Shah; John D. Davis; Ashley Saulsbury; Cong Fu; Venkatesh Iyengar; Jenn-Yuan Tsai; Jeff Gibson

Archive | 2005

Hardware demapping of TLBs shared by multiple threads

Paul J. Jordan; Manish K. Shah; Gregory F. Grohoski

Archive | 2005

Multiple-core processor with flexible mapping of processor cores to cache banks

Ricky C. Hetherington; Manish K. Shah; Gregory F. Grohoski; Bikram Saha

Archive | 2004

Out-of-order memory transactions in a fine-grain multithreaded/multi-core processor

Christopher H. Olson; Manish K. Shah

Archive | 2004

Cache error handling in a multithreaded/multi-core processor

Jama I. Barreh; Manish K. Shah

Archive | 2005

Demapping TLBs across physical cores of a chip

Paul J. Jordan; Manish K. Shah; Gregory F. Grohoski

Archive | 2009

BRANCH PREDICTION MECHANISM FOR PREDICTING INDIRECT BRANCH TARGETS

Manish K. Shah; Gregory F. Grohoski

Archive | 2005

Multithreaded processor having a source processor core to subsequently delay continued processing of demap operation until responses are received from each of remaining processor cores

Paul J. Jordan; Manish K. Shah; Gregory F. Grohoski

Archive | 2004

Optimizing hardware TLB reload performance in a highly-threaded processor with multiple page sizes

Greg Grohoski; Ashley Saulsbury; Paul J. Jordan; Manish K. Shah; Rabin A. Sugumar; Mark Debbage; Venkatesh Iyengar

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