nny K. F. Ma

X-Ray Inspection-Induced Latent Damage in DRAM

For quality verification, an X-ray inspection process is commonly being used for evaluating obscured and defective solder joints in surface mount technologies such as BGAs and flip chips. Integrated circuits subjected to any form of radiation, ionizing or non-ionizing, may incur some amount of damage depending on the absorbed dose. Though most X-ray inspections for high-quality imaging require ionizing dose amounts that are considered inconsequential for device failure or non-functionality, the degree of latent damage must be carefully considered. This paper discusses X-ray induced vulnerabilities of high-density DRAM exposed to low ionizing radiation levels typical in X-ray inspection systems. We look at critical parameters and their sensitivity in relation to varying dose amounts of X-ray irradiation. In consideration of different methodologies of reducing radiation dose amounts and limiting device exposure, we propose a procedure for attenuating potentially harmful X-ray radiation levels while preserving quality images

X-Ray Radiation Effect in DRAM Retention Time

For quality verification, an X-ray inspection process is commonly being used for evaluating obscured and defective solder joints in surface-mount technologies, such as ball grid arrays and flip chips. Integrated circuits subjected to any form of radiation, i.e., ionizing or nonionizing, may incur some amount of damage depending on the absorbed dose. Though most X-ray inspections for high-quality imaging require ionizing dose amounts that are considered inconsequential for device failure or non-functionality, the degree of latent damage must be carefully considered. This paper discusses X-ray-induced vulnerabilities of high-density dynamic random access memory exposed to low ionizing radiation levels typical in X-ray inspection systems. We look at critical parameters and their sensitivity in relation to varying dose amounts of X-ray irradiation. In consideration of different methodologies of reducing radiation dose amounts and limiting device exposure, we propose a procedure for attenuating potentially harmful X-ray radiation levels while preserving quality images.

Correlating Wafer-Level TDDB Lifetime Projections to HTOL Gate-Oxide Failures

The power-law model provides a relatively good correlation between the wafer-level (WL) time-dependent dielectric breakdown (TDDB) test (highly accelerated) conducted on test structures and high-temperature operating life (HTOL) test (moderately accelerated) conducted on product. This is true when WL stress is configured identically to HTOL stress, and the difference in oxide area between the two devices under stress is taken into account for lifetime projections.

Kinetic Analysis of X-Ray Irradiation Induced Static Refresh Failure Mechanism in DRAM

DRAM products are susceptible to low-dose X-ray irradiation with levels as low as 120 Rad(Si), much lower than previously reported values related to total ionizing dose (TID). A large variance in this susceptibility was observed among DRAM vendors. The key parameter affected by X-ray irradiation was static refresh, where the damage manifested as an increase in junction leakage of the storage node cell. Both junction leakage and gate-induced drain leakage currents (GIDL) were characterized, and results indicated that junction leakage was the dominant mechanism in static refresh (tref) degradation. The static refresh of both the extrinsic and intrinsic bit populations were affected by the low-dose ionizing radiation. However, in typical manufacturing X-ray inspection procedures, the tail bits can fall out of spec conditions and render the device a failure. Thermal annealing did lead to some recovery in tref; however, a complete recovery was not observed, even at high temperatures that may not be practical for components.

A highly reliable DRAM 3-D wafer thinning process

The mechanical properties of silicon substrate begin to deteriorate with the wafer thinning process particularly when thicknesses approach 50um or below. Key mechanical indexes such as Youngs modulus, hardness and fracture toughness are characterized by nanoindentation method to study the impact of thinning wafers on critical electrical parameters. It has been published that the lattice structure of Si substrate becomes highly distorted for wafer thicknesses below 50um. Depending on the magnitude of this distortion in the lattice structure, a reduction in Youngs modulus is generally observed. However, we demonstrate a thinning process that shows minimal impact on device reliability.