Mansour Jaragh

Engineering quicksort

This paper describes the results of a large empirical study to measure the run-time behavior of Quicksort by using various methods of computing the pivot element for medium to large size randomly generated integer data. The results of our study contradict the common notion that Quicksort gives best performance if median of three scheme is used to compute the pivot element and array partitions having 9% when compared to the method with a cutoff of 10 and sub-arrays with < 10 elements insertion sorted for 1000 =< N 1.5 x 10^6. Our study shows that advanced hardware features allow for implementation of very fast codes for sorting small arrays, and using such codes instead of insertion sort can lead to substantial improvements for Quicksort, as conjectured by Sedgewick many years ago.

Synthesis of communications protocol converters using the timed Petri net model

The proliferation of heterogeneous, distributed computer networks has led to an urgent need for constructing reliable and efficient communication protocol converter, to facilitate the internetworking between such networks. Most existing converter design methods are based on the communicating finite state machine (CFSM) model as the formal description technique to describe the protocols, their services and the converter design. Two drawbacks of CFSM model are the state explosion problem and the inability of the model to express concurrent behaviors of protocols and services. These drawbacks may be overcome by using Petri nets as the formal description technique. Moreover, a reliable converter must perform its conversion functions in a timely manner satisfying the timing constraints of both protocol architectures. Our paper adopts the Timed Petri net (TPN) model to fulfill this requirement. The paper also highlights the dynamicity of the derived converter. We illustrate the converter design method using an example showing the dynamicity and timeliness features of the converter. ” 1999 Elsevier Science Inc. All rights reserved.

Modeling communications protocols using the Unified Modeling Language

Specifying communications protocols is a very important step of the protocol development process and protocol engineering. A rigorous specification would result in a more reliable and highly maintainable implementation, and hence would reduce the time and cost required for performing the development and maintenance activities. In this paper, we propose the use of the Unified Modeling Language (UML) (Booch et al. 1999) for the specification documentation and elicitation of behavioral, structural and architectural models covering both the static and dynamic aspects of protocols. We illustrate the use of UML using a simple communication service and protocol.

A methodology for the synthesis of communication gateways for network interoperability

Abstract Because of the proliferation of proprietary network architectures and protocols, there is an urgent need for constructing communication gateways to ensure the interoperability among such networks and protocols. This interoperability will guarantee a wider access to value-added services and applications in todays information technology market. In this paper, we present a gateway synthesis method that considers the common services of two different proprietary protocols and services to obtain a gateway that can provide a transparent reconciliatory interface between the various networks. Our method starts by computing the greatest common service definition of two service definitions. Then, two sets of traces related to appropriate observation points are obtained and then synchronized. Finally, a synchronizing finite state machine converter is synthesized. An illustrative example is also provided.

Modeling computer hardware using the Unified Modeling Language

The design algorithm of computer hardware functional units constitutes a major step in the overall design of the system. It requires highly reliable modeling entities to illustrate the different intermediate stages to go from problem specification to the final system development. These stages constitute the behavioral as well as the functional aspect of the overall system. We illustrate the use of the Unified Modeling Language, UML, using a simple communication service and protocol. The different UML diagrams will be used to configure the system model. In particular, we start with the use case diagram and proceed to the final stage of the deployment stage A parallel to serial protocol converter is used to illustrate the method.

Synthesis of protocol converters: an annotated bibliography

Abstract The interoperability between heterogeneous, distributed computer networks requires the use of protocol converters. The need for constructing reliable and efficient communication protocol converters was due to the proliferation of such networks. Over a decade of intensive research and development has contributed greatly to the field of protocol conversion. Various formal approaches have been introduced to derive a converter in a systematic manner, the three most popular approaches being the service-level approach, the PDU-level approach and the hybrid approach. In this paper, we introduce protocol conversion and converter synthesis, and we briefly describe the main features of many proposed converter synthesis methods. Tables summarizing this bibliography are also provided.

Review paper: Synthesis of communications protocol converters: survey and assessment

The interoperability between heterogeneous, distributed computer networks requires the use of protocol converters. The need for constructing reliable and efficient communication protocol converters is caused by the proliferation of such networks. An efficient level of interoperability will guarantee a wider access to value-added services and applications in todays information technology. Over a decade of intensive research and development has contributed greatly to the field of protocol conversion. Various formal methods were introduced to derive a converter in a systematic manner. In this article, we survey and assess the research published on formal methods for deriving protocol converters over the past decade. We also provide some directions for future work in this area.

An empirical study of the run-time behavior of quicksort, shellsort and mergesort for medium to large size data

The paper describes the results of a large empirical study to measure the practical behavior of the basic versions of the popular internal sorting algorithms, Shellsort, quicksort, and mergesort, for medium to large size data and compares them with previous results. The results give running times of θ(N1.25) for Shellsort, quicksort, and mergesort for 1000 150,000. Quicksort outperforms both Shellsort and mergesort for all values of N > 1000. Our fits show better performance for Shellsort than the previous studies and are mostly accurate to within 2% for 1000 < N < 2 × 106. The primary reason for this error seems to be related to the error in the measured data.

A triangular systolic array for the discrete-time deconvolution

The principles of convolution and deconvolution known for linear systems have been applied to many engineering problems such as electromagnetic inverse scattering, seismology, system identifications, pattern recognition, etc. For applications involving a large amount of data, systolic array processing is attractive for efficiency and reduction of the data-processing time. Systolic arrays for discrete-time convolution have been previously developed. A triangular systolic array, consisting of two types of processing cells, is presented for the discrete-time deconvolution. The functions of the processing cells and their interconnections are described. The pipeline architecture of the triangular systolic array is derived from the recursive pattern of deconvolution. Cell computations and data flow within the systolic array are synchronized by a single global clock. >

Implementation, analysis and performance evaluation of the IRP replacement policy

As the processor speeds have improved significantly over the years, memory access penalties have become a major issue. The continuously growing gap between the processor and memory performance is making cache misses more and more expensive. In this paper, we suggest that the most common techniques currently implemented, such as least recently used (LRU) and most frequently used (LFU), are inadequate for current computer architectures as they do not complement each other and in many cases lead to the choice of the wrong line to replace. We propose the use of a more improved cache replacement policy technique in order to reduce the number of cache misses and optimise cache performance. Our solution, the improved replacement policy (IRP) merges the positive features in some of the most common policies and eliminates some of their prevalent drawbacks. IRP also employs the concept of spatial locality and therefore efficiently expels only blocks which are not likely to be accessed again. Finally, the IRP performance is compared to LRU and LFU methods.