Manuel Ortiz

Efficient Implementation of Carry-Save Adders in FPGAs

Most Field Programmable Gate Array (FPGA) devices have a special fast carry propagation logic intended to optimize addition operations. The redundant adders do not easily fit into this specialized carry-logic and, consequently, they require double hardware resources than carry propagate adders, while showing a similar delay for small size operands. Therefore, carry-save adders are not usually implemented on FPGA devices, although they are very useful in ASIC implementations. In this paper we study efficient implementations of carry-save adders on FPGA devices, taking advantage of the specialized carry-logic. We show that it is possible to implement redundant adders with a hardware cost close to that of a carry propagate adder. Specifically, for 16 bits and bigger wordlengths, redundant adders are clearly faster and have an area requirement similar to carry propagate adders. Among all the redundant adders studied, the 4:2 compressor is the fastest one, presents the best exploitation of the logic resources within FPGA slices and the easiest way to adapt classical algorithms to efficiently fit FPGA resources.

Efficient mapping on FPGA of convolution computation based on combined CSA-CPA accumulator

In this paper we present some architectures to deal with fast convolution computation based on carry save adders which are intended to be specifically implemented on FPGAs. Carry-save adders are not frequent in FPGA implementations since FPGA has a fast carry propagation path. In this paper we prove that it is possible to use carry-save arithmetic in a efficient way on FPGA for convolution operation. We make use of the specific structure of the FPGA to design an optimized accumulator which is able to deal with carry-save additions as well as carry-propagate additions using the same hardware. This lead to an efficient combined CSA-CPA architecture with fast computation and optimizing the hardware cost. Experimental results for different word lengths are presented to validate our proposal.

Smart Home Automation Using Controller Area Network

In several works, researches have recently proposed the use of a CAN bus (Controller Area Network) as a control network for smart home automation. The use of CAN for the lower network layers has advantages in the field of automation compared with networks based on RS485 due to its multimaster architecture. While compared with other common bus networks such as Ethernet or networks based on token passing, CAN has real time features and ease of implementation and programming of the nodes and therefore, a lower cost. This paper presents the study and evaluation of automation and remote control of an alarm system and HVAC system (Heating, Ventilation, and Air Conditioning) of a home, using CAN as a backbone network. The first version of TUCAN (Tuple Space and CAN) has been also used for the software of the nodes. TUCAN is a data-centric lightweight middleware that provides a CAN bus abstraction, and is based on the concept of Tuple Channel Space. A prototype with four nodes has been used to study the feasibility of the CAN bus as a single network and to evaluate TUCAN middleware.

CAN2PCI: Placa con Interfaz al Bus CAN y PCI con Finalidad Docente

In this work the development of a board with interface to the CAN and PCI bus for its use in lab courses related to control networks, is presented. This board has high benefits and advantages and has been implemented for educational purposes due to its programming facility. The board has two independent CAN channels and it allows direct access to the registers of the CAN controller. The objective of the lab experiments is to study the control networks in the physical and link levels and to develop a middleware that performs the interface between these layers and the user application. The experiments done in one of the courses, which includes control networks, are briefly described. In these practical labs it is very important the use of a known hardware that allows programming the basic functions which directly operate with the CAN bus controller.

DigitalLib: A VHDL library of basic blocks to automate the design of advanced digital systems

The objective of this work is the development of a library, named DigitalLib, of basic blocks of digital electronics described in VHDL language (as multiplexers, decoders, adders, subtractors, flip-flops, registers, memories, etc.), whose role is to facilitate and automate the design of advanced digital systems. In the developed blocks have been included parameters in order to adapt them to any size and precision. Hence, the implementation of advanced designs is based only on interconnecting the basic elements developed in the library, and assigning the appropriate parameters for each element. In order to demonstrate the simplification of designs with DigitalLib, which can be used by students of subjects of Advanced Design of Digital Systems, the work includes the description of different complex designs developed with this library.

Convolution Computation in FPGA Based on Carry-Save Adders and Circular Buffers

In this article, we present some architectures to carry out the convolution computation based on carry–save adders and circular buffers implemented on FPGAs. Carry-save adders are not frequent in the implementation in FPGA devices, since these have a fast carry propagation path. We make use of the specific structure of the FPGA to design an optimized accumulator which is able to deal with carry–save additions as well as carry–propagate additions using the same hardware. On the other hand, this structure of circular buffers allows the convolution computation of two signals with two algorithms of calculation: the input side algorithm and the output side algorithm, in a more efficient way.

UCORE: Reconfigurable Platform for Educational Purposes

This paper presents an educational platform for digital system practices with a conventional PCI bus interface, based on reconfigurable hardware especially useful for the designing of hardware accelerators and systems with a PCI bus interface. The aim of the platform is to provide students with a single tool to develop rapid prototypes that covers all aspects involved in the study of digital systems. The platform consists of hardware and software components that allow to easily develop prototypes of general electronic systems, simple systems with a conventional PCI bus interface, hardware accelerators, and buses. The platform is focused on reconfigurable computing practices for university degrees in Electronics Industrial Engineering and Computer Engineering of the new framework of European Higher Education Area (EHEA).

ADQPCI: Placa de Adquisición de Datos con Fines Docentes

In this work a data acquisition board developed for educational use in subjects related to real-time systems and industrial computing, is presented. The main advantages and disadvantages of using these boards versus the use of commercial boards are discussed. The hardware design described along this work emphasizes the facility of programming the board, which is one of the main advantages versus the commercial boards. In these practices it is essential that student comprehend the importance of the hardware-software interface in order to obtain a reliable system which exploits in a maximum way the characteristics of the hardware. The development of a data acquisition board allows to obtain a system that the students can use in several course during his university career which are related to the development and programming of embedded systems.

Using soft processors for component design in SOC: A case-study of timers

System on Chip (SOC) could be considered as a very useful alternative in the design of real-time systems, especially due to the possibility of integrating several processors in just one FPGA. This strategy enables the use of soft processors to design the systempsilas components, which have traditionally been developed by hardware. In this paper we study a HW/SW codesign of a timer pool for its use in SOC, which is constructed by a Picoblaze soft processor. Our approach offers a novel alternative among hardware and software timers that increases the overall system performance, and achieves a higher precision than software timers with a considerable reduction in cost and area occupied.