Marc Houdebine

A NEW FRACTIONAL FREQUENCY SYNTHESIZER ARCHITECTURE WITH STABILITY AND ROBUSTNESS ANALYSIS

Abstract This paper presents a new fractional frequency synthesizer architecture and its semi-global stability and robustness analysis tool. The proposed analysis tool takes into account the switched and non linear characteristics of the system components. In order to validate this study, simulation results were obtained with electronics simulators.

Nonlinear PLL Model for Simulation of Noise and Modulation Mixing in Polar Architecture

A nonlinear time domain model is presented for polar modulation transceiver chain sizing. The model inputs the phase modulation for WCDMA standard, but also any device noise of the PLL. Thanks to this model, a mixing phenomenon between modulation and Sigma-Delta brewing appears and is detailed in this paper. This mixing degrades EVM up to 13% in the case of 5MHz bandwidth WCDMA. As explained, this mixing cannot be simulated by linear frequency-domain models. Amplitude and Phase filtering added to the choose of a proper reference frequency can reduce the loss of EVM down to 5% which is not insignificant and underlines that the amplitude path is not the only critical path of polar architectures.

A sampled spur free fractional frequency synthesizer and its noise analysis

This paper presents a new fractional frequency synthesizer architecture and its noise analysis model. The proposed analysis model takes into account the sampled behavior of the PLL. In order to validate this study, measurement results illustrate the output frequency purity and the reliability of the model

An 85-GHz fully integrated all digital fractional frequency synthesizer for e-band backhaul and radar applications in 55-nm BiCMOS

This paper presents a fully integrated and spur-free fractional frequency synthesizer based on a low noise 42.5-GHz SiGe quad-core VCO locked on a standard 40-MHz crystal unit. Consequently, optimal SNR is obtained for narrow bandwidth. Reference spurs are below -80 dBc thanks to a programmable digital loop filter in the range of 0.5 kHz to 50 kHz. The PLL architecture digitally controls the phase offset for beam forming and linearizes the VCO to ensure constant cut-off frequency and optimal SNR. Contrary to two-point modulation which requires calibration, radar modulation is simply added in one point after loop filter and before VCO linearizer. These blocks - XO, PLL and frequency doubler - are packaged in a BGA substrate.