Marc Renaudin

An asynchronous NOC architecture providing low latency service and its multi-level design framework

The demands of scalable, low latency and power efficient system-on-chip interconnect cannot only be satisfied by point-to-point or shared-bus interconnects. In this paper, we propose a new asynchronous network-on-chip (NOC) architecture which provides low latency transfers. This architecture is implemented as a GALS system, where chip units are built as synchronous islands, connected together using a delay insensitive asynchronous network-on-chip topology. The proposed NOC protocol and its asynchronous implementation are presented as well as the multi-level modeling approach using SystemC language and transaction-level-modeling. Preliminary simulation results show that the asynchronous NOC can offer 5 Gbytes/s throughput in a 0.13 /spl mu/m CMOS technology.

A new class of asynchronous A/D converters based on time quantization

This work is a contribution to a drastic change in standard signal processing chains. The main objective is to reduce the power consumption by one or two orders of magnitude. Integrated Smart Devices and Communicating Objects are application domains targeted by this work. In this context, we present a new class of Analog-to-Digital Converters (ADCs), based on an irregular sampling of the analog signal, and an asynchronous design. Because they are not conventional, a complete design methodology is presented. It determines their characteristics given the required effective number of bits and the analog signal properties. it is shown that our approach leads to a significant reduction in terms of hardware complexity and power consumption. A prototype has been designed for speech applications, using the STMicroelectronics 0.18-/spl mu/m CMOS technology. Electrical simulations prove that the factor of merit is increased by more than one order of magnitude compared to synchronous Nyquist ADCs.

Asynchronous FIR filters: towards a new digital processing chain

This paper is a contribution to the definition of a new kind of digital signal processing chain. It is focused on Finite-Impulse-Response filtering (FIR) applied to irregularly sampled signals obtained from an asynchronous analog to digital converter. The paper first formalizes the convolution operator in the irregular sampling context. The computational complexity is deduced and compared to the one of standard synchronous FIR filters. It shows that a significant reduction of the computational complexity is achievable, hence a reduction in terms of energy. The paper then describes the architecture of the asynchronous filter. It finally reports the simulations performed on a speech application, resulting in a reduction of the processing power of about one order of magnitude.

Implementing Asynchronous Circuits on LUT Based FPGAs

This paper describes a general methodology to rapidly prototype asynchronous circuits on LUT based FPGAs. The main objective is to offer designers the powerfulness of standard synchronous FPGAs to prototype their asynchronous circuits or mixed synchronous/asynchronous circuits. To avoid hazard in FPGAs, the appearance of hazard in configurable logic cells is analyzed. The developed technique is based on the use and the design of a Muller gate library. It is shown how the place and route tools automatically exploit this library. Finally, an asynchronous dual-rail adder is implemented automatically to demonstrate the potential of the methodology. Several FPGA families, like Xilinx X4000, Altera Flex, Xilinx Virtex and uptodate Altera Apex are targeted.

Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic

This paper presents hardening techniques against fault attacks and the practical evaluation of their efficiency. The circuit technology investigated to improve the resistance against fault attacks is asynchronous logic. Specific properties of asynchronous circuits make them inherently resistant against a large class of faults. An analysis of their behavior in the presence of faults shows that they are an interesting alternative to design robust systems. A behavior diagnosis enables us to propose hardening techniques that improve fault tolerance and resistance. They are applied at design time and aim at exploiting quasi-delay insensitive (QDI) circuit properties to significantly harden the architecture with a very low area overhead and a reasonable performance penalty. To validate these techniques, a hardened DES crypto-processor is presented. The countermeasures are evaluated using laser beam fault injection

A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling

In systems-on-chip, dynamic voltage scaling allows energy savings. If only one global voltage is scaled down, the voltage cannot be lower than the voltage required by the most constrained functional unit to meet its timing constraints. Fine-grained dynamic voltage scaling allows better energy savings since each functional unit has its own independent clock and voltage, making the chip globally asynchronous and locally synchronous. In this paper we propose a local dynamic voltage scaling architecture, adapted to globally asynchronous and locally synchronous systems, based on a technique called Vdd-hopping. Compared to traditional power converters, the proposed power supply selector is small and power-efficient, with no needs for large passives or costly technological options. This design has been validated in a STMicroelectronics CMOS 65nm low-power technology.

ASPRO-216: a standard-cell Q.D.I. 16-bit RISC asynchronous microprocessor

The design of a CMOS standard-cell Quasi-Delay-Insensitive (QDI) 16-bit asynchronous microprocessor is presented. ASPRO-216 is being developed for embedded applications. It is a scalar processor which issues instructions in-order and completes their execution out-of-order, and it can be customized both at the hardware and software levels to fit specific application requirements. Its architecture extensively uses an overlapping pipelined execution scheme involving desynchronized units. The design flow and circuit style are an original application of A. Martins method. The expected performance is 200 peak MIPS, 0.5 Watt using a 0.25 /spl mu/m technology.

DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement

The paper formally specifies a flow devoted to the design of differential power analysis (DPA) resistant QDI (quasi delay insensitive) asynchronous circuits. The paper first proposes a formal modeling of the electrical signature of QDI asynchronous circuits. The DPA is then applied to the formal model in order to identify the source of leakage of this type of circuit. Finally, a complete design flow is specified to minimize the information leakage. The relevancy and efficiency of the approach is demonstrated using the design of an AES crypto-processor.

High security smartcards

New consumer appliances such as PDA, set top box, GSM/UMTS terminals enable an easy access to the Internet and strongly contribute to the development of e-commerce and m-commerce services. Tens of billion payments are made using cards today, and this is expected to grow in a near future. Smartcard platforms will enable operators and service providers to design and deploy new e- and m-commerce services. This development can only be achieved if a high level of security is guaranteed for the transactions and the customers information. In this context, smartcard design is very challenging in order to provide the flexibility and the powerfulness required by the applications and services, while at the same time guaranteeing the security of the transactions and the customers privacy. The goal of the session is to introduce this context and highlights the main challenges the smartcard designers/manufacturers have to face.

FPGA architecture for multi-style asynchronous logic [full-adder example]

This paper presents a novel FPGA architecture for implementing various styles of asynchronous logic. The main objective is to break the dependency between the FPGA architecture, dedicated to asynchronous logic, and the logic style. The innovative aspects of the architecture are described. Moreover, the structure is well suited to be rebuilt and adapted to fit with further asynchronous logic evolutions, thanks to the architecture genericity. A full-adder was implemented in different styles of logic to show the architecture flexibility.