Marc Rocchi

Realistic statistical worst-case simulations of VLSI circuits

A simple and cost-effective method for evaluating the parametric product manufacturability of VLSI circuits is presented. The method, named gradient analysis, enables designers to predict the standard deviation of the circuit performance from measured or specified design parameter variations. This method, with a minimum extra design cost, avoids the overdesign associated with the traditional prediction of the worst-case performance of VLSI circuits. Gradient analysis also provides designers with information on the sensitivity of the circuit performance variations to the design parameter variations. In this way the key design parameters for process monitoring and control are identified. Experimental qualification of the method is discussed based on development and production data of VLSI products such as high-speed 1.2 mu m 64 K CMOS static RAMs (SRAMs),. >

Statistical parameter control for optimum design and manufacturability of VLSI circuits

A first-order statistical worst-case design methodology for VLSI products that is based on uncorrelated groups of geometry- and temperature-independent design parameters has been developed. The parameters are statistically monitored in production by extending in-line SPC (statistical process control) to PCM results. Key groups of design parameters are identified by means of a complete sensitivity analysis (including second-order terms and cross terms if necessary) on the performance parameters within the parameter windows. An estimate of the 3- sigma performance limits is then readily derived from the results of the sensitivity analysis. The uncorrelated groups of geometry- and temperature-independent design parameters have been found to be an optimum interface between process and design, making statistical design possible in a very cost-effective way. Experimental qualification of the method is discussed based on development and production data of a high-speed 1.2- mu m 64 K CMOS SRAM.<<ETX>>

A 200-GHz True E-Mode Low-Noise MHEMT

In this paper, a fully passivated true enhancement mode 110-nm metamorphic high-electron mobility transistor (E-MHEMT) on GaAs substrate with excellent dc and RF performance has been developed. By choosing an indium content of 40% for the AlInAs/GalnAs/AlInAs MHEMT, the difference between the Schottky-barrier height and the conductance band-offset (channel/barrier) of the device is enhanced compared with 53% indium devices lattice matched to an InP substrate. A true E-MHEMT is demonstrated with an extremely low leakage current, wide gate-voltage swing, and excellent dynamic performance. The threshold-voltage standard deviation is only 12 mV on four wafers. The device presents an excellent unity gain cutoff frequency of 204 GHz with state-of-the-art NFmin = 0.69 dB and Gass = 10 dB at 30 GHz. This transistor is a good candidate for high-speed digital, high-frequency analog, or mixed applications, where the low noise, low-power consumption, and digital capabilities of this technology are distinct advantages.

GaAs MMICs for Cordless and Cellular Telecommunications: The Fight Against Silicon Odds

For a few years now the civil market for GaAs MMICs has budded into application niches such as 12 GHz DBS dowinconverters. The next large application niche which is rapidly emerging concerns low voltage L-band receive and transmit front-ends for cordless and cellular phones. In spite of forceful Silicon slurs, some GaAs MMICs have already made their way into coimmercially available handsets for GSM 900 MHz and DECT 1900 MHz standards. Tlis is readily accounted for by the swift change in the mobile market needs and the respective availability of low cost GaAs & Silicon RF IC products. After a thorough analysis of the low voltage performance, low cost and low weight requirements derived from handset specifications, an optimum RF front-end partitioning between Silicon and GaAs can be determined resulting in an optimumn RF cHip set.

A Novel Approach to Realistic Worst-case Simulations of CMOS Circuits

To enhance the design of CMOS circuits a new method, named Gradient Analysis, has been proposed and verified. Gradient Analysis enables designers to realistically predict the standard deviation of the circuit performance from measured or guesstimated device parameter variations. It is realistic both in terms of its accuracy and in terms of the number of simulation runs required. With as few as one simulation run the approach is shown to accurately predict the variation of 64K SRAMs Read Access Time and Low Level Output Voltage. Gradient Analysis also provides designers with information on the sensitivity of the circuit performance variations to the device parameter variations.

GaAs & Si MMIC Building Blocks: a moot point revisited

The emergence of large volume markets for commercial space and ground telecommunication systems is beginning to reignite the smouldering Si-GaAs controversy mainly limited so far to high speed digital applications. The main difference now is that GaAs IC processes and especially N-off mixed a/d processes like PMI s PR07AD, have matured into commercially available products. More specifically they yield a better cost-performance trade-off than their Si counterparts down to L-band when low noise and low DC power is the issue. Basic GaAs analogue-digital building blocks like LNAs, active mixers, VCOs, PLLs and power modules are available today, either as standard ICs or as standard cells for ASIC design. Very low DC power Fully and high packing density monolithic downconverters including an RF LNA, mixer and a VCO can thus be designed with 4.5 dB NF and 20 dB associated gain at 1.9 GHz and a drain current as low as 4 mA at Vdd - 3 V for a chip area as small as 0.5 mm2.

Theoretical and experimental temperature dependence of GaAs N-off IC's over 120 K to 400 K

Abstract A temperature dependent CAD MESFET model has been developed for GaAs N-off ICs. Experimental verification of the model for temperature ranging from 120 K to 400 K have been made on various circuits. Less than 10 % difference between simulation and experiment has been found up to 370°K.

GaAs PHEMT CHIP SETS AND IC PROCESSES FOR HIGH-END FIBER OPTIC APPLICATIONS

Continuous improvement of high bit rate fiber optic networking up to 40 Gb/s, results in increased demand for III/V ICs offering ever lower current input noise, higher output voltage swing, lower jitter and lower DC power consumption. Using production E/D and power sub 0,2 μm GaAs PHEMT processes, transimpedance amplifiers have been developed enabling optical input sensitivity as good as -25 dBm at 2.5 Gb/s and -20 dBm at 40 Gb/s. Similarly laser and modulator drivers have been fabricated with jitter as low as 1,8 ps rms at 10 Gb/s and over 7 V output swing up to 40 GHz. Future generations of products will be implemented using sub 0,1 μm processes based on E/D and power GaAs MHEMTs as well as InP HEMTs maintaining a long tern performance edge over the Silicon counterparts.

New leaf for Philips

Your article about Plesseys Caswell laboratories (April, Focus p12) mentions Philips (LEP) as a technically excellent but commercially weak GaAs IC vendor.

A 2.5 ns, 40 mW, 4 × 4 GaAs Multiplier in 2's Complement Mode

INTRODUCTION Arithmetic aña* memory VHS I Cs will be required, in the near future for Gb/s processing systems. In order to reach high speed, low power performances and satisfy real world system specifications, a GaAs parallel multiplier of two signed (2s complement coded), 4 bit words has been designed and fabricated using a 1 um N-OFF MESFET process. The circuit consists of conventional DCFL gates and transfer logic cells. A modified Booths Algorithm has thus been implemented for the first time in GaAs, showing the high design flexibility of N-OFF MESFETs. A 2.5 ns multiplying time has been achieved with an associated power consumption of 40 mW, for a complexity of 213 equivalent gates.