Marcel Beemster

Back-end aspects of a portable POOL-X implementation

The paper discusses an implementation of POOL-X that aims to be all of available, reliable, portable, modifiable and efficient. This implementation consists of both compiler and run-time-support system. In order to attain the stated goals, the system is kept as simple as possible. Design trade-offs are be discussed, and the final system is evaluated.

The CAMAS workbench: computer aided migration of applications system

A simulation methodology for predicting the performance of sequential programs as well as data parallel (SPMD) programs on parallel and distributed platforms is presented. The proposed methodology comprises a parameterised description of the applications as well as the target machines. An integrated simulation procedure estimates the time complexity of the (SPMD) application given a well-defined hardware platform and predicts the execution behaviour. The methodology has been actualised in terms of a toolset currently under development at the University of Amsterdam.

Strictness optimization for graph reduction machines (why id might not be strict)

Strictness optimizations in the implementation of lazy functional languages are not always valid. In nonoptimized graph reduction, evaluation always takes place at the request of case analysis or a primitive operation. Hence, the result of a reduction is always a data value and never a function. This implies that in an implementation no argument satisfaction check is required. But in the presence of strict arguments, “premature” reduction may take place outside the scope of a case or primitive operation. This causes problems in graph reducers that use an aggressive take. Two solutions are presented, one based on a run-time argument satisfaction check, the other on a weakened strictness analyzer. Experimental results are used to compare the two solutions and show that the cost of the aggressive take can be arbitrarily high for specific programs. The experimental results enable a trade-off to be made by the reduction machine designer.

Experience with a clustered parallel reduction machine

A clustered architecture has been designed to exploit divide and conquer parallelism in functional programs. The programming methodology developed for the machine is based on explicit annotations and program transformations. It has been successfully applied to a number of algorithms resulting in a benchmark of small and medium size parallel functional programs. Sophisticated compilation techniques are used such as strictness analysis on non-flat domains and RISC and VLIW code generation. Parallel jobs are distributed by an efficient hierarchical scheduler. A special processor for graph reduction has been designed as a basic block for the machine. A prototype of a single cluster machine has been constructed with stock hardware. This paper describes the experience with the project and its current state.