Marcel Profirescu

Quantum transport in submicron devices

The paper presents both conceptual and computational features of quantum transport in semiconductor nanostructures. The results comprise microelectronic structures (MOSFETs, heterojunction devices) where the quantum effects count as well as nanometer-sized semiconductor structures.

MOSFET distorsion analysis including series resistance modelling aspects

The new challenge of nanotechnology needs very accurate models for active devices. From this point of view the design of linear analog circuits lacks models for state-of-the-art MOS transistors to accurately describe distortion effects. This is mainly due to inaccurate modelling of the second order effects such as mobility degradation due to high vertical gate field, velocity saturation in the channel and short channel series resistance. After a rigorous description of series resistance components we included the series resistance in the MOS transistor model and used a compact expression of series resistance for computation reasons. The simulations using the new series resistance expression were in good agreement with experimental data.

MOSFET mobility degradation modelling

The design of linear analog circuits lacks models for state-of-the-art MOS transistors to accurately describe distortion effects. This is mainly due to inaccurate modelling of the mobility degradation effect i.e. the dependence of carrier mobility in the inversion layer on the normal electric (gate) field. A new mobility relation in agreement with experiment was obtained using quantum mechanical transport analysis.

An active switch improved Dickson Charge Pump implemented in a BCD process

The paper presents a new improved integrated charge pump based on the use of both enhanced and depletion MOS transistors as active switches and charge transfer devices in order to accommodate the voltage class requirements specific to the BCD technology. A two stage design was implemented using 2.5 MHz clock frequency to drive the charge pump capacitors.

Carrier mobility and series resistance MOSFET modeling

The scaling-down evolution of semiconductor devices will ultimately attend fundamental limits as transistor reach the nanoscale aria. In this context the MOSFET models must give the process variations and the relevant characteristics like current, conductance, transconductance, capacitances, flicker thermal or high frequency noise and distortion. The new challenge of nanotechnology needs very accurate models for active devices. The design of linear analog circuits lacks models for state-of-the-art MOS transistors to accurately describe distortion effects. This is mainly due to inaccurate modelling of the mobility degradation effect i.e. the dependence of carrier mobility in the inversion layer on the gate normal electric field. For short-channel devices the influence of series resistance becomes important and depends on the gate voltage. The drain current expression incorporating a new mobility relation obtained from quantum mechanical transport analysis and the series resistance influence is in good agreement with experiment.

Pilot implementation of a web-based microelectronics laboratory within EDIT Distance Learning Network

The paper describes the way of implementing online laboratory work using a web-based approach. This pilot implementation was done within the EDIT Distance Learning Network using the asynchronous and synchronous facilities of the LOTUS learning space 4.01 distance learning environment.

Ensemble Monte Carlo Simulation of a Pseudomorpihc HEMT Structure

The paper presents an analysis of a pseudomorphic HEMT structure through an ensemble Monte Carlo simulation. The effect of velocity overshoot and real-space transfer on the device performance is investigated. The electron drift velocity drops due to the intervalley transfer in the bulk InGaAs, and real-space transfer into the surrounding lower mobility GaAs and AlGaAs layers. Depending on the gate bias, the velocity near the drain is limited by either k-space or real-space transfer. At low gate bias real-space transfer occurs, while at high gate bias intervalley transfer within the bulk InGaAs limits the carrier speeds.

Electro-Thermal Simulation Environment for Digital ICs

The paper presents a digital simulation environment at gate level circuit modeling for both functional and thermal behavior. It focuses on the thermal model implementation in Verilog using language extensions.

Neural network technique for the speed-up of Monte-Carlo based semiconductor simulators

The paper presents a way for improving the simulation time of the Monte-Carlo based simulators using a neural network structure. A multi-layered feed-forward neural network trained with a quasi-Newton algorithm was used. As an example, the extraction of the bulk transport parameters of a III-V compound semiconductor is discussed.