Marco Benedetti

A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test

Many CAD for VLSI techniques use time-frame expansion, also known as the iterative logic array representation, to model the sequential behavior of a system. Replicating industrial-size designs for many time-frames may impose impractically excessive memory requirements. This work proposes a performance-driven, succinct and parametrizable quantified Boolean formula (QBF) satisfiability encoding and its hardware implementation for modeling sequential circuit behavior. This encoding is then applied to three notable CAD problems, namely bounded model checking (BMC), sequential test generation and design debugging. Extensive experiments on industrial circuits confirm outstanding run-time and memory gains compared to state-of-the-art techniques, promoting the use of QBF in CAD for VLSI.

Robust QBF Encodings for Sequential Circuits with Applications to Verification, Debug, and Test

Formal CAD tools operate on mathematical models describing the sequential behavior of a VLSI design. With the growing size and state-space of modern digital hardware designs, the conciseness of this mathematical model is of paramount importance in extending the scalability of those tools, provided that the compression does not come at the cost of reduced performance. Quantified Boolean Formula satisfiability (QBF) is a powerful generalization of Boolean satisfiability (SAT). It also belongs to the same complexity class as many CAD problems dealing with sequential circuits, which makes it a natural candidate for encoding such problems. This work proposes a succinct QBF encoding for modeling sequential circuit behavior. The encoding is parametrized and further compression is achieved using time-frame windowing. Comprehensive hardware constructions are used to illustrate the proposed encodings. Three notable CAD problems, namely bounded model checking, design debugging and sequential test pattern generation, are encoded as QBF instances to demonstrate the robustness and practicality of the proposed approach. Extensive experiments on OpenCore circuits show memory reductions in the order of 90 percent and demonstrate competitive runtimes compared to state-of-the-art SAT techniques. Furthermore, the number of solved instances is increased by 16 percent. Admittedly, this work encourages further research in the use of QBF in CAD for VLSI.

Modeling adversary scheduling with QCSP

We consider cumulative scheduling problems in the presence of an adversary. In such setting the scheduler tries to manage the available resources in so as to meet the scheduling deadline, while the adversary is allowed to change some parameters---like the resource consumption of some tasks---up to a certain limit. We ask whether a robust schedule exists, i.e., one that is guaranteed to work whatever (malicious) actions the opponent may take. We propose to model this family of decision problems using a variant of Quantified Constraint Satisfaction Problems called QCSP+, and to solve them by using the solver QeCode.