Marco G. Pala

Strain-Induced Performance Improvements in InAs Nanowire Tunnel FETs

This paper investigates the electrical performance improvements induced by appropriate strain conditions in n-type InAs nanowire tunnel FETs in the context of a systematic comparison with strained silicon MOSFETs. To this purpose, we exploited a 3-D simulator based on an eight-band k p Hamiltonian within the nonequilibrium Green function formalism. Our model accounts for arbitrary crystal orientations and describes the strain implicitly by a modification of the band structure. The effect of acoustic- and optical-phonon scattering is also accounted for in the self-consistent Born approximation. Our results show that appropriate strain conditions in n-type InAs tunnel FETs induce a remarkable enhancement of Ion with a small degradation of the subthreshold slope, as well as large improvements in the Ioff versus Ion tradeoff for low Ioff and VDD values. Hence, an important widening of the range of Ioff and VDD values where tunnel FETs can compete with strained silicon MOSFETs is obtained.

Interface Traps in InAs Nanowire Tunnel-FETs and MOSFETs—Part I: Model Description and Single Trap Analysis in Tunnel-FETs

This paper and the companion work present a full quantum study of the influence of interface traps on the I-V characteristics of InAs nanowire Tunnel-field effect transistors (FETs) and MOSFETs. To this purpose, we introduced a description of interface traps in a simulator based on non equilibrium Greens function formalism, employing an 8 × 8 k·p Hamiltonian and accounting for phonon-scattering. In our model, traps can affect the I-V curves of the transistors both by modifying the device electrostatics and by directly participating the carrier transport. This paper investigates the impact of single trap on the I-V characteristics of Tunnel-FETs by varying the trap energy level, its volume and position, as well as the working temperature. Our 3-D self-consistent simulations show that: 1) even a single trap can deteriorate the inverse subthreshold slope of a nanowire InAs Tunnel-FET; 2) shallow traps have the largest impact on subthreshold slopes; and 3) the inelastic phonon-assisted tunneling through interface traps results in a temperature dependence of the otherwise temperature-independent Tunnel-FETs I-V characteristics.

Phonon- and surface-roughness-limited mobility of gate-all-around 3C-SiC and Si nanowire FETs

We present numerical simulations of gate-all-around (GAA) 3C-SiC and Si nanowire (NW) field effect transistors (FETs) using a full quantum self-consistent Poisson-Schrödinger algorithm within the non-equilibrium Greens function (NEGF) formalism. A direct comparison between Si and 3C-SiC device performances sheds some light on the different transport properties of the two materials. Effective mobility extraction has been performed in a linear transport regime and both phonon- (PH) and surface-roughness-(SR) limited mobility values were computed. 3C-SiC FETs present stronger acoustic phonon scattering, due to a larger deformation potential, resulting in lower phonon-limited mobility values. Although Si NW devices reveal a slightly better electrostatic control compared to 3C-SiC ones, SR-limited mobility shows a slower degradation with increasing charge density for 3C-SiC devices. This implies that the difference between Si and 3C-SiC device mobility is reduced at large gate voltages. 3C-SiC nanowires, besides their advantages compared to silicon ones, present electrical transport properties that are comparable to the Si case.

Surface-Roughness-Induced Variability in Nanowire InAs Tunnel FETs

We present a comparative study of the surfaceroughness (SR)-induced variability at low supply voltage VDD = 0.3 V in nanowire InAs tunnel FETs and strained-silicon (sSi) MOSFETs. By exploiting a 3-D full-quantum approach based on the Non-Equilibrium Greens Function formalism, we show that the Ion variability in InAs tunnel FETs is much smaller than the Ioff variability, whereas for VDD = 0.3 V, the sSi MOSFETs working in the subthreshold regime present similar Ion and Ioff variability. We explain the smaller Ion compared with Ioff variability of InAs tunnel FETs by noting that in the source depletion region, where tunneling mainly occurs for VGS = VDD, microscopic subband fluctuations induced by SR are small compared to macroscopic band bending due to the built-in potential of the source junction and to the gate bias. This results in SR-induced variability that is larger in InAs tunnel FETs than in sSi MOSFETs.

Three-Dimensional Real-Space Simulation of Surface Roughness in Silicon Nanowire FETs

We address the transport properties of narrow gate-all-around silicon nanowires in the presence of surface-roughness (SR) scattering at the Si/SiO2 interface, considering nanowire transistors with a cross section of 3 times 3 nm2 and gate length of 15 nm. We present transfer characteristics and effective-mobility calculations based on a full 3-D real-space self-consistent Poisson-Schrodinger solver within the nonequilibrium Greens function formalism. The effect of SR is included via a geometrical method consisting in a random realization of potential fluctuations described via an exponential autocorrelation law. The influence on transfer characteristics and on low-field mobility is evaluated by comparison with the clean case and for different values of the root mean square of potential fluctuations. The method allows us to exactly account for mode-mixing and subband fluctuations and to evaluate the effect of SR up to all orders of the interaction. We find that SR scattering is mainly responsible for positive threshold-voltage shift in the low-field regime, whereas SR-limited mobility slowly depends on the linear charge density, showing the inefficiency of mode-mixing scattering mechanism for very narrow wires.

Channel-Length Dependence of Low-Field Mobility in Silicon-Nanowire FETs

We investigate the role of two main scattering mechanisms responsible for mobility degradation in ultrashort electron devices like silicon-nanowire FETs. We consider electron-phonon interaction and surface roughness (SR) at the Si/SiO2 interface as sources of inelastic and elastic scatterings. We address a full-quantum treatment within the nonequilibrium Greens function formalism, which allows us to take quantum confinement, quantum-phase interference, out of equilibrium, and quasi-ballistic transport into account. Our results show that both phonon- and SR-limited mobilities strongly depend on the channel length due to the importance of nonuniform scattering in ultrashort devices and contribute to understand the strong mobility reduction of decananometric devices.

Interface Traps in InAs Nanowire Tunnel FETs and MOSFETs—Part II: Comparative Analysis and Trap-Induced Variability

This paper extends the analysis of the companion paper by presenting a comparative analysis of the impact of interface traps on the I-V characteristics of InAs nanowire tunnel FETs or MOSFETs with a spatially random distribution of traps. The physical mechanisms behind the effects of traps in either tunnel FETs or MOSFETs are compared and, furthermore, traps are also investigated as a possible source of device variability. Our results show that, in MOSFETs, an aggressive oxide thickness scaling can effectively counteract the degradation of the subthreshold slope (SS) possibly produced by interface traps. Tunnel FETs are instead more vulnerable to traps, which are probably the main hindrance to the experimental realization of tunnel FETs with an SS better than 60 mV/decade.

Spin-orbit coupling and phase-coherence in InAs nanowires

We investigated the magnetotransport of InAs nanowires grown by selective area metal-organic vapor phase epitaxy. In the temperature range between 0.5 and 30 K reproducible fluctuations in the conductance upon variation of the magnetic field or the back-gate voltage are observed, which are attributed to electron interference effects in small disordered conductors. From the correlation field of the magnetoconductance fluctuations the phase-coherence length lis determined. At the lowest temperatures lis found to be at least 300 nm, while for temperatures exceeding 2 K a monotonous decrease of lwith temperature is observed. A direct observation of the weak antilocalization effect indicating the presence of spin-orbit coupling is masked by the strong magnetoconductance fluctua- tions. However, by averaging the magnetoconductance over a range of gate voltages a clear peak in the magnetoconductance due to the weak antilocalization effect was resolved. By comparison of the experimental data to simulations based on a recursive two-dimensional Greens function approach a spin-orbit scattering length of approximately 70 nm was extracted, indicating the presence of strong spin-orbit coupling.

Imaging electron wave functions inside open quantum rings

Combining scanning gate microscopy (SGM) experiments and simulations, we demonstrate low temperature imaging of the electron probability density |Psi|(2)(x,y) in embedded mesoscopic quantum rings. The tip-induced conductance modulations share the same temperature dependence as the Aharonov-Bohm effect, indicating that they originate from electron wave function interferences. Simulations of both |Psi|(2)(x,y) and SGM conductance maps reproduce the main experimental observations and link fringes in SGM images to |Psi|(2)(x,y).

On the imaging of electron transport in semiconductor quantum structures by scanning-gate microscopy: successes and limitations

This paper presents a brief review of scanning-gate microscopy applied to the imaging of electron transport in buried semiconductor quantum structures. After an introduction to the technique and to some of its practical issues, we summarize a selection of its successful achievements found in the literature, including our own research. The latter focuses on the imaging of GaInAs-based quantum rings both in the low-magnetic-field Aharonov-Bohm regime and in the high-field quantum Hall regime. Based on our own experience, we then discuss in detail some of the limitations of scanning-gate microscopy. These include possible tip-induced artefacts, effects of a large bias applied to the scanning tip, as well as consequences of unwanted charge traps on the conductance maps. We emphasize how special care must be paid in interpreting these scanning-gate images.