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Dive into the research topics where Marco Lapegna is active.

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Featured researches published by Marco Lapegna.


PPAM (2) | 2016

Virtualizing CUDA Enabled GPGPUs on ARM Clusters

Raffaele Montella; Giulio Giunta; Giuliano Laccetti; Marco Lapegna; Carlo Palmieri; Carmine Ferraro; Valentina Pelliccia

The acceleration of inexpensive ARM-based computing nodes with high-end CUDA enabled GPGPUs hosted on x86 64 machines using the GVirtuS general-purpose virtualization service is a novel approach to hierarchical parallelism. In this paper we draw the vision of a possible hierarchical remote workload distribution among different devices. Preliminary, but promising, performance evaluation data suggests that the developed technology is suitable for real world applications.


International Journal of Parallel Programming | 2012

A Double Adaptive Algorithm for Multidimensional Integration on Multicore Based HPC Systems

Giuliano Laccetti; Marco Lapegna; Valeria Mele; Diego Romano; Almerico Murli

In this work, a parallel double adaptive algorithm for the computation of a multidimensional integral on multicore based multicomputer systems is described. This new algorithm is the revision of a procedure developed by one of the present authors for multicomputer systems, with the aim to introduce features for an efficient implementation in multicore based hierarchical environments. Two different adaptive strategies have been combined together in the algorithm: a first procedure is responsible for load balancing among the system nodes and a second one is responsible for coordinating the cores within a single node. The performance is analyzed and experimental results on a Blade Server with 8 nodes and 2 quad-core CPUs per node have been achieved.


International Journal of Parallel Programming | 2017

On the Virtualization of CUDA Based GPU Remoting on ARM and X86 Machines in the GVirtuS Framework

Raffaele Montella; Giulio Giunta; Giuliano Laccetti; Marco Lapegna; Carlo Palmieri; Carmine Ferraro; Valentina Pelliccia; Cheol-Ho Hong; Ivor T. A. Spence; Dimitrios S. Nikolopoulos

The astonishing development of diverse and different hardware platforms is twofold: on one side, the challenge for the exascale performance for big data processing and management; on the other side, the mobile and embedded devices for data collection and human machine interaction. This drove to a highly hierarchical evolution of programming models. GVirtuS is the general virtualization system developed in 2009 and firstly introduced in 2010 enabling a completely transparent layer among GPUs and VMs. This paper shows the latest achievements and developments of GVirtuS, now supporting CUDA 6.5, memory management and scheduling. Thanks to the new and improved remoting capabilities, GVirtus now enables GPU sharing among physical and virtual machines based on x86 and ARM CPUs on local workstations, computing clusters and distributed cloud appliances.


parallel, distributed and network-based processing | 2003

Integrating MPI-based numerical software into an advanced parallel computing environment

Pasqua D'Ambra; Marco Danelutto; Daniela di Serafino; Marco Lapegna

In this paper we present first experiences concerning the integration of MPI-based numerical software into an advanced programming environment for building parallel and distributed high-performance applications, which is under development in the context of Italian national research projects. Such a programming environment, named ASSIST, is based on a combination of the concepts of structured parallel programming and component-based programming. Some activities within the projects are devoted to the definition, implementation and testing of a methodology for the integration of a parallel numerical library into ASSIST. The goal is providing a set of efficient, accurate and reliable tools that can be easily used as building blocks for high-performance scientific applications. We focus on the integration of existing and widely used MPI-based numerical library modules. To this aim, we propose a general approach to embed MPI computations into the ASSIST basic programming unit. This approach has been tested using the MPICH implementation of MPI for networks of workstations. Some modifications have been applied to the MPICH process startup procedure, in order to make it compliant with the ASSIST environment. Results of experiments concerning the integration of routines from a well-known FFT package are discussed.


european conference on parallel processing | 1999

PAMIHR. A Parallel FORTRAN Program for Multidimensional Quadrature on Distributed Memory Architectures

Giuliano Laccetti; Marco Lapegna

PAMIHR: a parallel adaptive routine for the approximate computation of a multidimensional integral over a hyperrectangular region is described. The software is designed to efficiently run on a MIMD distributed memory environment, and its based on the widely diffused communication system BLACS. PAMIHR, further, gives special attention to the problems of scalability and of load balancing among the processes.


international conference on parallel processing | 2013

A study on adaptive algorithms for numerical quadrature on heterogeneous GPU and multicore based systems

Giuliano Laccetti; Marco Lapegna; Valeria Mele; Diego Romano

In this work, a parallel adaptive algorithm for the computation of a multidimensional integral on heterogeneous GPU and multicore based systems is described. Two different strategies have been combined together in the algorithm: a first procedure is responsible for the load balancing among the threads on the multicore CPU and a second one is responsible for an efficient execution on the GPU of the computational kernel. The performance is analyzed and experimental results on a system with a quad-core CPUs and two GPUs have been achieved.


Concurrency and Computation: Practice and Experience | 2017

Accelerating Linux and Android applications on low-power devices through remote GPGPU offloading

Raffaele Montella; Sokol Kosta; David Oro; Javier Vera; Carles Fernández; Carlo Palmieri; Diana Di Luccio; Giulio Giunta; Marco Lapegna; Giuliano Laccetti

Low‐power devices are usually highly constrained in terms of CPU computing power, memory, and GPGPU resources for real‐time applications to run. In this paper, we describe RAPID, a complete framework suite for computation offloading to help low‐powered devices overcome these limitations. RAPID supports CPU and GPGPU computation offloading on Linux and Android devices. Moreover, the framework implements lightweight secure data transmission of the offloading operations. We present the architecture of the framework, showing the integration of the CPU and GPGPU offloading modules. We show by extensive experiments that the overhead introduced by the security layer is negligible. We present the first benchmark results showing that Java/Android GPGPU code offloading is possible. Finally, we show the adoption of the GPGPU offloading into BioSurveillance, a commercial real‐time face recognition application. The results show that, thanks to RAPID, BioSurveillance is being successfully adapted to run on low‐power devices. The proposed framework is highly modular and exposes a rich application programming interface to developers, making it highly versatile while hiding the complexity of the underlying networking layer.


international conference on parallel processing | 2017

Using GPGPU Accelerated Interpolation Algorithms for Marine Bathymetry Processing with On-Premises and Cloud Based Computational Resources

Livia Marcellino; Raffaele Montella; Sokol Kosta; Ardelio Galletti; Diana Di Luccio; Vincenzo Santopietro; Mario Ruggieri; Marco Lapegna; Luisa D’Amore; Giuliano Laccetti

Data crowdsourcing is one of most remarkable results of pervasive and internet connected low-power devices making diverse and different “things” as a world wide distributed system. This paper is focused on a vertical application of GPGPU virtualization software exploitation targeted on high performance geographical data interpolation. We present an innovative implementation of the Inverse Distance Weight (IDW) interpolation algorithm leveraging on CUDA GPGPUs. We perform tests in both physical and virtualized environments in order to demonstrate the potential scalability in production. We present an use case related to high resolution bathymetry interpolation in a crowdsource data context.


International Journal of Parallel Programming | 2017

An Approach to Forecast Queue Time in Adaptive Scheduling: How to Mediate System Efficiency and Users Satisfaction

Giovanni Battista Barone; Vania Boccia; Davide Bottalico; Rosanna Campagna; Luisa Carracciuolo; Giuliano Laccetti; Marco Lapegna

The minimisation of the total cost of ownership is hard to be faced by the owners of large scale computing systems, without affecting negatively the quality of service for the users. Modern datacenters, often included in distributed environments, appear to be “elastic”, i.e., they are able to shrink or enlarge the number of local physical or virtual resources, also by recruiting them from private/public clouds. This increases the degree of dynamicity, making the infrastructure management more and more complex. Here, we report some advances in the realisation of an adaptive scheduling controller (ASC) which, by interacting with the datacenter resource manager, allows an effective and an efficient usage of resources. In particular, we focus on the mathematical formalisation of the ASC’s kernel that allows to dynamically configure, in a suitable way, the datacenter resources manager. The described formalisation is based on a probabilistic approach that, starting from both a hystorical resources usage and on the actual users request of the datacenter resources, identifies a suitable probability distribution for queue time with the aim to perform a short term forecasting. The case study is the SCoPE datacenter at the University of Naples Federico II.


International Journal of Parallel Programming | 2016

A Loosely Coordinated Model for Heap-Based Priority Queues in Multicore Environments

Giuliano Laccetti; Marco Lapegna; Valeria Mele

Heap-based priority queues are very common dynamical data structures used in several fields, ranging from operating systems to scientific applications. However, the rise of new multicore CPUs introduced new challenges in the process of design of these data structures: in addition to traditional requirements like correctness and progress, the scalability is of paramount importance. It is a common opinion that these two demands are partially in conflict each other, so that in these computational environments it is necessary to relax the requirements of correctness and linearizability to achieve high performances. In this paper we introduce a loosely coordinated approach for the management of heap based priority queues on multicore CPUs, with the aim to realize a tradeoff between efficiency and sequential correctness. The approach is based on a sharing of information among only a small number of cores, so that to improve performance without completely losing the features of the data structure. The results obtained on a scientific problem show significant benefits both in terms of parallel efficiency, as well as in term of numerical accuracy.

Collaboration


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Giuliano Laccetti

University of Naples Federico II

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Raffaele Montella

University of Naples Federico II

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Valeria Mele

University of Naples Federico II

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Diego Romano

Indian Council of Agricultural Research

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Carlo Palmieri

Parthenope University of Naples

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Giulio Giunta

Parthenope University of Naples

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Almerico Murli

University of Naples Federico II

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Carmine Ferraro

Parthenope University of Naples

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Daniela di Serafino

Seconda Università degli Studi di Napoli

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