Marcus Yip

A Resolution-Reconfigurable 5-to-10-Bit 0.4-to-1 V Power Scalable SAR ADC for Sensor Applications

A power-scalable SAR ADC for sensor applications is presented. The ADC features a reconfigurable 5-to-10-bit DAC whose power scales exponentially with resolution. At low resolutions where noise and linearity requirements are reduced, supply voltage scaling is leveraged to further reduce the energy-per-conversion. The ADC operates up to 2 MS/s at 1 V and 5 kS/s at 0.4 V, and its power scales linearly with sample rate down to leakage levels of 53 nW at 1 V and 4 nW at 0.4 V. Leakage power-gating during a SLEEP mode in between conversions reduces total power by up to 14% at sample rates below 1 kS/s. Prototyped in a low-power 65 nm CMOS process, the ADC in 10-bit mode achieves an INL and DNL of 0.57 LSB and 0.58 LSB respectively at 0.6 V, and the Nyquist SNDR and SFDR are 55 dB and 69 dB respectively at 0.55 V and 20 kS/s. The ADC achieves an optimal FOM of 22.4 fJ/conversion-step at 0.55 V in 10-bit mode. The combined techniques of DAC resolution and voltage scaling maximize efficiency at low resolutions, resulting in an FOM that increases by only 7x over the 5-bit scaling range, improving upon a 32x degradation that would otherwise arise from truncation of bits from an ADC of fixed resolution and voltage.

A resolution-reconfigurable 5-to-10b 0.4-to-1V power scalable SAR ADC

Applications such as sensor networks and medical monitoring often require ADCs that can digitize signals with varying bandwidth and dynamic range requirements. In energy-constrained systems, it is beneficial to adapt the ADC performance to the signal to avoid consuming power on unnecessary bandwidth or accuracy. Therefore, this paper presents a single reconfigurable SAR ADC whose power scales with resolution and sample rate to improve energy efficiency, while reducing system complexity and cost.

A Biomedical Sensor Interface With a sinc Filter and Interference Cancellation

A compact, low-power, digitally-assisted sensor interface for biomedical applications is presented. It exploits oversampling and mixed-signal feedback to reduce system area and power, while making the system more robust to interferers. Antialiasing is achieved using a charge-sampling filter with a sinc frequency response and programmable gain. A mixed-signal feedback loop creates a sharp, programmable notch for interference cancellation. A prototype was implemented in a 0.18-μm CMOS process. The on-chip blocks operate from a 1.5-V supply and consume between 255 nW and 2.5 μW depending on noise and bandwidth requirements.

A Fully-Implantable Cochlear Implant SoC With Piezoelectric Middle-Ear Sensor and Arbitrary Waveform Neural Stimulation

A system-on-chip for an invisible, fully-implantable cochlear implant is presented. Implantable acoustic sensing is achieved by interfacing the SoC to a piezoelectric sensor that detects the sound-induced motion of the middle ear. Measurements from human cadaveric ears demonstrate that the sensor can detect sounds between 40 and 90 dB SPL over the speech bandwidth. A highly-reconfigurable digital sound processor enables system power scalability by reconfiguring the number of channels, and provides programmable features to enable a patient-specific fit. A mixed-signal arbitrary waveform neural stimulator enables energy-optimal stimulation pulses to be delivered to the auditory nerve. The energy-optimal waveform is validated with in-vivo measurements from four human subjects which show a 15% to 35% energy saving over the conventional rectangular waveform. Prototyped in a 0.18 μm high-voltage CMOS technology, the SoC in 8-channel mode consumes 572 μW of power including stimulation. The SoC integrates implantable acoustic sensing, sound processing, and neural stimulation on one chip to minimize the implant size, and proof-of-concept is demonstrated with measurements from a human cadaver ear.

A flexible pressure monitoring system for pressure ulcer prevention

Pressure ulcers are painful sores that arise from prolonged exposure to high pressure points, which restricts blood flow and leads to tissue necrosis. This is a common occurrence among patients with impaired mobility, diabetics and the elderly. In this work, a flexible pressure monitoring system for pressure ulcer prevention has been developed. The prototype consists of 99 capacitive pressure sensors on a 17-cm×22-cm sheet which is flexible in two dimensions. Due to its low cost, the sensor sheet can be disconnected from the reusable electronics and be disposed of after use, suitable for a clinical setting. Each sensor has a resolution of better than 2-mmHg and a range of 50-mmHg and offset is calibrated in software. Realtime pressure data is displayed on a computer. A maximum sampling rate of 12-Hz allows for continuous monitoring of pressure points.

Design of Low-Voltage Digital Building Blocks and ADCs for Energy-Efficient Systems

Increasing number of energy-limited applications continue to drive the demand for designing systems with high energy efficiency. This tutorial covers the main building blocks of a system implementation including digital logic, embedded memories, and analog-to-digital converters and describes the challenges and solutions to designing these blocks for low-voltage operation.

A 0.6V 2.9µW mixed-signal front-end for ECG monitoring

This paper presents a mixed-signal ECG front-end that uses aggressive voltage scaling to maximize power-efficiency and facilitate integration with low-voltage DSPs. 50/60Hz interference is canceled using mixed-signal feedback, enabling ultra-low-voltage operation by reducing dynamic range requirements. Analog circuits are optimized for ultra-low-voltage, and a SAR ADC with a dual-DAC architecture eliminates the need for a power-hungry ADC buffer. Oversampling and ΔΣ-modulation leveraging near-VT digital processing are used to achieve ultra-low-power operation without sacrificing noise performance and dynamic range. The fully-integrated front-end is implemented in a 0.18μm CMOS process and consumes 2.9μW from 0.6V.

18.2 A fully-implantable cochlear implant SoC with piezoelectric middle-ear sensor and energy-efficient stimulation in 0.18μm HVCMOS

A cochlear implant (CI) is a device that electrically stimulates the auditory nerve to restore hearing in people with profound hearing loss. Conventional CIs rely on an external unit comprising a microphone and sound processor to pick up and encode sound. The external unit raises concerns with social stigma and limits usage in the shower or during water sports, motivating the need for a fully-implantable (i.e., invisible) cochlear implant (FICI). The limited energy storage capacity of the implanted system requires low-power (<;1mW total power) sound processing and auditory nerve stimulation to enable operation from an implanted battery that is wirelessly recharged only once daily. Recent state-of-the-art ICs are typically designed for external microphone-based CIs and do not require the neural stimulator to be on the same chip [1]. Prior implantable acoustic sensors such as accelerometers sense the sound-induced vibration of the middle ear, but this approach has limited sensitivity and requires several mW of power for the sensor itself [2].

Energy-efficient waveform for electrical stimulation of the cochlear nerve

The cochlear implant (CI) is the most successful neural prosthesis, restoring the sensation of sound in people with severe-to-profound hearing loss by electrically stimulating the cochlear nerve. Existing CIs have an external, visible unit, and an internal, surgically-placed unit. There are significant challenges associated with the external unit, as it has limited utility and CI users often report a social stigma associated with prosthesis visibility. A fully-implantable CI (FICI) would address these issues. However, the volume constraint imposed on the FICI requires less power consumption compared to today’s CI. Because neural stimulation by CI electrodes accounts for up to 90% of power consumption, reduction in stimulation power will result directly in CI power savings. To determine an energy-efficient waveform for cochlear nerve stimulation, we used a genetic algorithm approach, incorporating a computational model of a single mammalian myelinated cochlear nerve fiber coupled to a stimulator-electrode-tissue interface. The algorithm’s prediction was tested in vivo in human CI subjects. We find that implementation of a non-rectangular biphasic neural stimulation waveform may result in up to 25% charge savings and energy savings within the comfortable range of hearing for CI users. The alternative waveform may enable future development of a FICI.