Marek Gorgon

PixelStreams-based implementation of videodetector

This paper introduces a method that enhances the relocatability of partial bitstreams for FPGA run-time reconfiguration. Reconfigurable applications usually employ partial bitstreams which are specific to one target region on the FPGA. Previously, techniques have been proposed that allow relocation between identical regions on the FPGA. However, as FPGAs are becoming increasingly heterogeneous, this approach is often too restrictive. We introduce a method that circumvents the problem of having to find fully identical regions based on compatible subsets of resources, enabling flexible placement of relocatable modules. In a software defined radio prototype with two reconfigurable regions, the number of partial bitstreams is reduced by 50% and the compile time is shortened by 43%.In the present paper the background generation and motion detection algorithms, which are of key importance for the implementation of video detection, have been presented. A modification of the background generation algorithm, essential for proper algorithm functioning at medium and high road-traffic conditions, has been proposed. Algorithm adaptation for the implementation in reprogrammable device has been also presented. PixelStream-based implementation has been successfully performed. Real-time verification on reconfigurable platform has been done.

Handel-C implementation of classical component labelling algorithm

In the paper the implementation of classical label component algorithm in Handel-C language has been discussed. The implementation of the image segmentation stage has been realized in real-time in the pipeline structure. The process of construction of optimal implementation has been shown, including the algorithm parallelization on one hand and taking advantage of the language features on the other. Each implementation has been verified in hardware and tested by a set of specially designed test images.

Floating point HOG implementation for real-time multiple object detection

Object detection and localization in a video stream is an important requirement for almost all vision systems. In the article a design embedded into a reconfigurable device which is using the Histogram of Oriented Gradients for feature extraction and SVM classification for detecting multiple objects is presented. Superior accuracy is achieved by making all computations using single precision 32-bit floating point values in all stages of image processing. The resulting implementation is fully pipelined and there is no need for external memory. Finally a working system able to detect and localize three different classes of objects in color images with resolution 640×480 @ 60fps is presented with a computational performance above 9 GFLOPS.

Real-time moving object detection for video surveillance system in FPGA

FPGA devices are a perfect platform for implementing image processing algorithms. In the article, an advanced video system is presented, which is able to detect moving objects in video sequences. The detection method is using two algorithms. First of all, a multimodal background generation method allows reliable scene modelling in case of rapid changes in lighting conditions and small background movement. Finally a segmentation based on three parameters lightness, colour and texture is applied. This approach allows to remove shadows from the processed image. Authors proposed some improvements and modifications to existing algorithms in order to make them suitable for reconfigurable platforms. In the final system only one, low cost, FPGA device is able to receive data from high speed digital camera, perform a Bayer transform, RGB to CIE Lab colour space conversion, generate a moving object mask and present results to the operator in real-time.

FPGA-based Road Traffic Videodetector

In the present paper the background generation and motion detection algorithms, which are of key importance for the implementation of videodetection, have been presented. A modification of the background generation algorithm, essential for proper algorithm functioning at medium and high road-traffic conditions, has been proposed. Algorithm adaptation for the implementation in reprogrammable device has been also presented. A modification of the SAD algorithm, used in motion detection, has been introduced. The modification allows for regions of interest of irregular shape and structure in the analyzed image. It creates a capability to conduct the calculations in independent and parallel manner for specific, user-defined, active videodetection regions. PixelStream-based implementation has been successfully performed. Real-time verification on reconfigurable platform has been done.

Efficient Hardware Implementation of the Horn-Schunck Algorithm for High-Resolution Real-Time Dense Optical Flow Sensor

This article presents an efficient hardware implementation of the Horn-Schunck algorithm that can be used in an embedded optical flow sensor. An architecture is proposed, that realises the iterative Horn-Schunck algorithm in a pipelined manner. This modification allows to achieve data throughput of 175 MPixels/s and makes processing of Full HD video stream (1, 920 × 1, 080 @ 60 fps) possible. The structure of the optical flow module as well as pre- and post-filtering blocks and a flow reliability computation unit is described in details. Three versions of optical flow modules, with different numerical precision, working frequency and obtained results accuracy are proposed. The errors caused by switching from floating- to fixed-point computations are also evaluated. The described architecture was tested on popular sequences from an optical flow dataset of the Middlebury University. It achieves state-of-the-art results among hardware implementations of single scale methods. The designed fixed-point architecture achieves performance of 418 GOPS with power efficiency of 34 GOPS/W. The proposed floating-point module achieves 103 GFLOPS, with power efficiency of 24 GFLOPS/W. Moreover, a 100 times speedup compared to a modern CPU with SIMD support is reported. A complete, working vision system realized on Xilinx VC707 evaluation board is also presented. It is able to compute optical flow for Full HD video stream received from an HDMI camera in real-time. The obtained results prove that FPGA devices are an ideal platform for embedded vision systems.

REAL-TIME IMPLEMENTATION OF MOVING OBJECT DETECTION IN VIDEO SURVEILLANCE SYSTEMS USING FPGA

The article presents the concept of real-time implementation computing tasks in video surveillance systems. A pipeline implementation of a multimodal background generation algorithm for colour video stream and a moving objects segmentation based on brightness, colour and textural information in reconfigurable resources of FPGA device is described. System architecture, resource usage and segmentation results are presented.

Pipeline implementation of the 128-bit block cipher CLEFIA in FPGA

The article presents a pipeline implementation of the block cipher CLEFIA. The article examines three known methods of implementing a single encryption round and proposes a new fourth method. The article proposes the implementation of a key scheduler, which is highly compatible with pipeline encryption. The article contains a detailed analysis of the data processing path for the 128-bit key version of the algorithm and verifies its operation on two FPGA cards in practice. On the basis of one of these cards, the article proposes a prototype of an effective supercomputer-compatible hardware accelerator (High Performance Computing Application).

FPGA based controller for heterogenous image processing system

In the present paper construction of a controller is described, which is used to control the RETINA image processing platform. The 32-bit RETINA card is dedicated to be used for image acquisition, processing and analysis. The module resources include Video ADC, Virtex FPGA device, floating point Motorola 96002 DSP and PCI Master interface, what enables the execution of all the operations in real-time. Controller is the main control centre for the module, supervising the modes and phases of its operation, and it is also used as a arbiter for the modules communication resources.

Automatically controlled pan-tilt smart camera with FPGA based image analysis system dedicated to real-time tracking of a moving object

An intelligent, automatically controlled camera based on visual feedback.A system for acquisition, processing image analysis and a camera driver are implemented in the FPGA Xilinx Spartan-6 device.The FPGA device is connected directly to the eight independently operated SRAM memory banks.A prototype device has been constructed with a real-time tracking algorithm.The camera is able to keep a tracked object close to the center of its field of view. This paper presents an intelligent, automatically controlled camera based on visual feedback. The camera housing contains actuators that change the orientation of the camera - enabling a full rotation around the vertical axis (pan) and 90? around the horizontal axis (tilt). A system for acquisition, processing image analysis and a camera driver are implemented in the FPGA Xilinx Spartan-6 device. An original, innovative reconfigurable system architecture has been developed. The FPGA device is connected directly to the eight independently operated SRAM memory banks. A prototype device has been constructed with a real-time tracking algorithm, enabling an automatically control of the position of the camera. The device has been tested indoors and outdoors. The camera is able to keep a tracked object close to the center of its field of view. The power consumption of the control system is 2W. A reconfigurable part reaches the computing performance of 3200 MOPS.