Marek Kraft

An evaluation of image feature detectors and descriptors for robot navigation

The detection and matching of feature points is crucial in many computer vision systems. Successful establishing of points correspondences between concurrent frames is important in such tasks as visual odometry, structure from motion or simultaneous localization and mapping. This paper compares of the performance of the well established, single scale detectors and descriptors and the increasingly popular, multiscale approaches.

An Indoor RGB-D Dataset for the Evaluation of Robot Navigation Algorithms

The paper presents a RGB-D dataset for development and evaluation of mobile robot navigation systems. The dataset was registered using a WiFiBot robot equipped with a Kinect sensor. Unlike the presently available datasets, the environment was specifically designed for the registration with the Kinect sensor. Moreover, it was ensured that the registered data is synchronized with the ground truth position of the robot. The presented dataset will be made publicly available for research purposes.

Calibration of the Multi-camera Registration System for Visual Navigation Benchmarking

This paper presents the complete calibration procedure of a multi-camera system for mobile robot motion registration. Optimization-based, purely visual methods for the estimation of the relative poses of the motion registration system cameras, as well as the relative poses of the cameras and markers placed on the mobile robot were proposed. The introduced methods were applied to the calibration of the system and the quality of the obtained results was evaluated. The obtained results compare favourably with the state of the art solutions, allowing the use of the considered motion registration system for the accurate reconstruction of the mobile robot trajectory and to register new datasets suitable for the benchmarking of indoor, visual-based navigation algorithms.

System on chip coprocessors for high speed image feature detection and matching

Successful establishing of point correspondences between consecutive image frames is important in tasks such as visual odometry, structure from motion or simultaneous localization and mapping. In this paper, we describe the architecture of the compact, energy-efficient dedicated hardware processors, enabling fast feature detection and matching.

A High-performance FPGA-based Image Feature Detector and Matcher Based on the FAST and BRIEF Algorithms

Image feature detection and matching is a fundamental operation in image processing. As the detected and matched features are used as input data for high-level computer vision algorithms, the matching accuracy directly influences the quality of the results of the whole computer vision system. Moreover, as the algorithms are frequently used as a part of a real-time processing pipeline, the speed at which the input image data are handled is also a concern. The paper proposes an embedded system architecture for feature detection and matching. The architecture implements the FAST feature detector and the BRIEF feature descriptor and is capable of establishing key point correspondences in the input image data stream coming from either an external sensor or memory at a speed of hundreds of frames per second, so that it can cope with most demanding applications. Moreover, the proposed design is highly flexible and configurable, and facilitates the trade-off between the processing speed and programmable logic resource utilization. All the designed hardware blocks are designed to use standard, widely adopted hardware interfaces based on the AMBA AXI4 interface protocol and are connected using an underlying direct memory access (DMA) architecture, enabling bottleneck-free inter-component data transfers.

Morphological Edge Detection Algorithm and Its Hardware Implementation

Mathematical morphology is a widely known image processing technique. Morphology-based processing techniques can be easily implemented, thanks to conceptual simplicity of basic morphological operators. However, most morphological algorithms that are run on sequential processors are unable to meet real-time requirements. A way to solve this problem are the implementations using dedicated hardware, e.g. the FPGAs.

Toward evaluation of visual navigation algorithms on RGB-D data from the first- and second-generation Kinect

Although the introduction of commercial RGB-D sensors has enabled significant progress in the visual navigation methods for mobile robots, the structured-light-based sensors, like Microsoft Kinect and Asus Xtion Pro Live, have some important limitations with respect to their range, field of view, and depth measurements accuracy. The recent introduction of the second- generation Kinect, which is based on the time-of-flight measurement principle, brought to the robotics and computer vision researchers a sensor that overcomes some of these limitations. However, as the new Kinect is, just like the older one, intended for computer games and human motion capture rather than for navigation, it is unclear how much the navigation methods, such as visual odometry and SLAM, can benefit from the improved parameters. While there are many publicly available RGB-D data sets, only few of them provide ground truth information necessary for evaluating navigation methods, and to the best of our knowledge, none of them contains sequences registered with the new version of Kinect. Therefore, this paper describes a new RGB-D data set, which is a first attempt to systematically evaluate the indoor navigation algorithms on data from two different sensors in the same environment and along the same trajectories. This data set contains synchronized RGB-D frames from both sensors and the appropriate ground truth from an external motion capture system based on distributed cameras. We describe in details the data registration procedure and then evaluate our RGB-D visual odometry algorithm on the obtained sequences, investigating how the specific properties and limitations of both sensors influence the performance of this navigation method.

The Architecture of an Embedded Smart Camera for Intelligent Inspection and Surveillance

Real time video surveillance and inspection is complex task, requiring processing large amount of image data. Performing this task in each node of a multi-camera system requires high performance and power efficient architecture of the smart camera. Such solution, based on a Xilinx Zynq heterogeneous FPGA (Field Programmable Logic Array) is presented in this paper. The proposed architecture is a general foundation, which allows easy and flexible prototyping and implementation of a range of image and video processing algorithms. Two example algorithm implementations using the described architecture are presented for illustration – moving object detection and feature points detection, description and matching.

FPGA implementation of the robust essential matrix estimation with RANSAC and the 8-point and the 5-point method

This paper presents a FPGA-based multiprocessor system for the essential matrix estimation from a set of point correspondences containing outliers. The estimation is performed using two methods: the 8-point and the 5-point algorithm, and complemented with robust estimation. The description of the architecture and the hardware-specific design considerations are given. Performance and resource use depending on the chosen method and the number of processing cores are also given.

DESIGN OF THE SPIKING NEURON HAVING LEARNING CAPABILITIES BASED ON FPGA CIRCUITS

Abstract Hardware real-time implementations of Spiking Neuron Networks (SNN) are wanted for multiple applications. Introduction of the supervised learning mechanism for SNNs is a hot topic. A model of a single spiking neuron having that property is proposed. This is based on LIF simplified model. A number of design issues has been solved in order to enable the correct work of such a neuron during earning phase. The proposed extensions and modifications are described and illustrated with corresponding timing diagrams.