Maria Liz Crespo

BORA: a front end board, with local intelligence, for the RICH detector of the Compass Collaboration

Abstract In this paper we describe the design of the re-configurable front-end boards (BORA boards) for the 82944 channel RICH-1 (Ring Imaging CHerenkov) of the Compass Collaboration (NA58). The front-end electronics controls the sample-and-hold operation after the arrival of an event trigger, acquires the analog voltages from the pre-amp VLSI and converts them into 10 bits at a rate of 20xa0Ms/s per analog channel. The digitized analogue values are then written into FIFOs. A subsequent operation compares the readings of each and every channel with corresponding programmable thresholds, and transmits those values larger than the threshold, together with the channel number, through an optical fiber to subsequent processing stages of the acquisition system. The overall operation of the board is controlled and supervised by a fast DSP. The availability of local intelligence allows the board to present innovative features such as: to be part of a computer network that connects several similar boards of the detector with a PC. The presence of the DSP allows testing the operability and linearity of the analog channels; and creating engineering frames containing local temperatures and voltages and transmitting the results through the network. The operator can reconfigure the hardware and software of the board by downloading programs from the PC.

A Block-Based Open Source Approach for a Reconfigurable Virtual Instrumentation Platform Using FPGA Technology

Recent advances in field-programmable gate arrays (FPGA) have made it possible to efficiently build various complex hardware emulation systems. This technology promises new levels of system integration onto a single FPGA, but also presents significant challenges to designers. The proposed reconfigurable virtual instrumentation (RVI) project leverages the latest FPGA technological advances. Its goal is to provide a low-cost reusable hardware/software platform for the emulation of multiple electronic and scientific instrumentation systems. Unlike previous approaches, the proposed architecture leverages a block-based design methodology that emphasizes design reuse as an effective mean to cope with the challenge of a growing design complexity. An open source approach to the project allows future contributors to rely on previously developed software, making the emulation of new instruments increasingly more cost-effective. This paper details the architecture of the RVI system with its main building blocks. It also illustrates its capabilities with multiple implementation examples

Building an Evolvable Low-Cost HW/SW Educational Platform--Application to Virtual Instrumentation

This paper describes a hardware/software FPGA-based platform. Its goal is to provide a reusable low-cost system for teaching system-level design, with an emphasis on design reuse as an effective mean to cope with an ever growing design complexity. An open source strategy promotes cross-university collaboration by relying on previously developed software. The first implementation examples target the area of Reconfigurable Virtual Instrumentation (RVI), which in turn provides a low-cost solution for teaching electronic instrumentation.

Development and tests of a new prototype detector for the XAFS beamline at Elettra Synchrotron in Trieste

The XAFS beamline at Elettra Synchrotron in Trieste combines X-ray absorption spectroscopy and X-ray diffraction to provide chemically specific structural information of materials. It operates in the energy range 2.4-27 keV by using a silicon double reflection Bragg monochromator. The fluorescence measurement is performed in place of the absorption spectroscopy when the sample transparency is too low for transmission measurements or the element to study is too diluted in the sample. We report on the development and on the preliminary tests of a new prototype detector based on Silicon Drift Detectors technology and the SIRIO ultra low noise front-end ASIC. The new system will be able to reduce drastically the time needed to perform fluorescence measurements, while keeping a short dead time and maintaining an adequate energy resolution to perform spectroscopy. The custom-made silicon sensor and the electronics are designed specifically for the beamline requirements.

A programmable System-on-Chip based digital pulse processing for high resolution X-ray spectroscopy

It is described the global architecture of a digital pulse processing system for high resolution X-Ray spectroscopy based on single photon detection and photon energy measurement. The core of the system is implemented in a modern hybrid device (Xilinx Zynq) that integrates an FPGA fabric along with a dual core 32-bits processor (ARM Cortex). It is also described the adopted strategy to deal with high input photon rates while preserving a good energy resolution. The digital performance of the system is ultimate determined by few key functional blocks including two finite impulse response filters and an algorithmic state machine. It is presented a numerical procedure to optimize the digital filters according to different constrains and goals, and it is described the analysis of experimental data to obtain the necessary information for the optimization of the system.

HyperFPGA: A possible general purpose reconfigurable hardware for custom supercomputing

In this work we propose and analyze a possible hardware architecture for experimentation on fine-grained reconfigurable supercomputing based on modern Field Programmable Gate Array (FPGA) technology. It is proposed a scalable cubic array of elementary computational units which are interconnected according to a tridimensional toroidal mesh network. Each computational unit is essentially formed by an FPGA plus an onboard external RAM memory. While the adjacent units in the bulk are directly interconnected through the regular FPGA IOs; the external units at opposite faces of the cubic array are interconnected by mean of high speed serial links in order to grant homogeneous data transfer bandwidth among all topologically adjacent units. Among several relevant issues we discuss the feasibility, scalability and portability.

HiCCE-128: An open hardware FMC module for High-Channel Count Electrophysiology

Electrophysiology has recently evolved into an interactive, high-throughput endeavor. Recording from dozens to hundreds of electrodes is today routine; novel means of manipulating the system in real time, through electrical stimulation, optogenetics or sensory manipulation are allowing us to decipher neural circuit function at an unparalleled rate. To contribute to the wide dissemination of such techniques, we present an open hardware project, High-Channel Count Electrophysiology (HiCCE), aiming to produce low-cost, high-channel count (≥128 channels) electrophysiology instrumentation capable of fast data acquisition rates, real-time processing and feedback capabilities. Our design is centered on an open standard, FPGA Mezzanine Card (FMC), which permits a varied choice of FPGA carrier architectures suited to different laboratory experimental needs. The HiCCE-128, a low-cost highperformance 128-channel data acquisition board for small voltage signals, is being introduced. It is a FMC module that can be operated from any FPGA carrier conforming to the FMC/VITA57 standard. This specialized board with a low input referred noise of about 3 μV is capable of acquiring 128 channels simultaneously at 31.25 kS/s per channel with 16 effective bits of resolution. We present the global architecture and some preliminary measurement to illustrate its potential for electrophysiological and medical applications.