Mariano López-García

Embedded System for Biometric Online Signature Verification

This paper describes the implementation on field-programmable gate arrays (FPGAs) of an embedded system for online signature verification. The recognition algorithm mainly consists of three stages. First, an initial preprocessing is applied on the captured signature, removing noise and normalizing information related to horizontal and vertical positions. Afterwards, a dynamic time warping algorithm is used to align this processed signature with its template previously stored in a database. Finally, a set of features are extracted and passed through a Gaussian Mixture Model, which reveals the degree of similarity between both signatures. The algorithm was tested using a public database of 100 users, obtaining high recognition rates for both genuine and forgery signatures. The implemented system consists of a vector floating-point unit (VFPU), specifically designed for accelerating the floating-point computations involved in this biometric modality. Moreover, the proposed architecture also includes a microprocessor, which interacts with the VFPU, and executes by software the rest of the online signature verification process. The designed system is capable of finishing a complete verification in less than 68 ms with a clock rated at 40 MHz. Experimental results show that the number of clock cycles is accelerated by a factor of ×4.8 and ×11.1, when compared with systems based on ARM Cortex-A8 and when substituting the VFPU by the Floating-Point Unit provided by Xilinx, respectively.

Real-Time Speaker Verification System Implemented on Reconfigurable Hardware

Nowadays, biometrics is considered as a promising solution in the market of security and personal verification. Applications such as financial transactions, law enforcement or network management security are already benefitting from this technology. Among the different biometric modalities, speaker verification represents an accurate and efficient way of authenticating a person’s identity by analyzing his/her voice. This identification method is especially suitable in real-life scenarios or when a remote recognition over the phone is required. The processing of a signal of voice, in order to extract its unique features, that allows distinguishing an individual to confirm or deny his/her identity is, usually, a process characterized by a high computational cost. This complexity imposes that many systems, based on microprocessor clocked at hundreds of MHz, are unable to process samples of voice in real-time. This drawback has an important effect, since in general, the response time needed by the biometric system affects its acceptability by users. The design based on FPGA (Field Programmable Gate Arrays) is a suited way to implement systems that require a high computational capability and the resolution of algorithms in real-time. Besides, these devices allow the design of complex digital systems with outstanding performance in terms of execution time. This paper presents the implementation of a MFCC (Mel-Frequency Cepstrum Coefficients)—SVM (Support Vector Machine) speaker verification system based on a low-cost FPGA. Experimental results show that our system is able to verify a person’s identity as fast as a high-performance microprocessor based on a Pentium IV personal computer.

SVM speaker verification system based on a low-cost FPGA

Biometric systems, characterized by their high confidential levels of security, are usually based on high-performance microprocessors implemented on personal computers. These advanced devices contain floating-point units able to carry out millions of operations per second at frequencies in the GHz range, being qualified to resolve the most complex algorithms in just a few hundred of milliseconds. However, their main drawback is the cost, and the necessary space required to incorporate their external associated peripherals. This disadvantage is especially significant in the low-cost consumer market, where factors such as price and size determine the viability of a product. The use of an FPGA is a suited way to implement systems that require a high computational capability at affordable prices. Besides, these devices allow the design of complex digital systems with outstanding performances in terms of execution times. This paper presents the implementation of a SVM (Support Vector Machines) speaker verification system on a low-cost FPGA. Experimental results show as our system is able to verify a persons identity as fast as a high-performance microprocessor based on a Pentium IV personal computer.

A new countermeasure against side-channel attacks based on hardware-software co-design

This paper aims at presenting a new countermeasure against Side-Channel Analysis (SCA) attacks, whose implementation is based on a hardware-software co-design. The hardware architecture consists of a microprocessor, which executes the algorithm using a false key, and a coprocessor that performs several operations that are necessary to retrieve the original text that was encrypted with the real key. The coprocessor hardly affects the power consumption of the device, so that any classical attack based on such power consumption would reveal a false key. Additionally, as the operations carried out by the coprocessor are performed in parallel with the microprocessor, the execution time devoted for encrypting a specific text is not affected by the proposed countermeasure. In order to verify the correctness of our proposal, the system was implemented on a Virtex 5 FPGA. Different SCA attacks were performed on several functions of AES algorithm. Experimental results show in all cases that the system is effectively protected by revealing a false encryption key.

Inverse Filtering Approximation for Impacting Signals Estimation Using a Multilayer Neural Network

This paper describes an original method for estimating impacting signals through an inverse filter based on a multilayer neural network (NN). A model for the impacting analytical signal has been used for training the NN using the Levenberg-Marquardt (LM) learning algorithm. The method has been tested with data acquired with a single-input accelerometer. Experimental results show that with the correct number of neurons and the proper training the NN can be used as an inverse filter

Hardware Architecture Implemented on FPGA for Protecting Cryptographic Keys against Side-Channel Attacks

This paper presents a new hardware architecture designed for protecting the key of cryptographic algorithms against attacks by side-channel analysis (SCA). Unlike previous approaches already published, the fortress of the proposed architecture is based on revealing a false key. Such a false key is obtained when the leakage information, related to either the power consumption or the electromagnetic radiation (EM) emitted by the hardware device, is analysed by means of a classical statistical method. In fact, the trace of power consumption (or the EM) does not reveal any significant sign of protection in its behaviour or shape. Experimental results were obtained by using a Virtex 5 FPGA, on which a 128-bit version of the standard AES encryption algorithm was implemented. The architecture could easily be extrapolated to an ASIC device based on standard cell libraries. The system is capable of concealing the real key when various attacks are performed on the AES algorithm, using two statistical methods which are based on correlation, the Welchs t-test and the difference of means.

Flexible Biometric Online Speaker-Verification System Implemented on FPGA Using Vector Floating-Point Units

This paper presents the implementation of a speaker-verification system on field programmable gate array. The algorithm is executed by software over an embedded system that includes a MicroBlaze microprocessor connected to a vector floating-point unit (VFPU). The VFPU is designed to speed up the resolution of any vector floating-point operation involved in the verification algorithm, whereas the microprocessor manages the control of the process and executes the rest of operations. With a clock frequency of 40 MHz, the system is capable of executing the complete algorithm in real time, processing a voice frame in 9.1 ms. The same verification process was carried out for two different systems: 1) an ARM Cortex A8 microprocessor; and 2) configuring MicroBlaze with the scalar floating-point unit provided by Xilinx. The experimental results show that when comparing our proposed system against both systems, the number of clock cycles is reduced by a factor of 11.2× and 15.4×, respectively. The main advantage of the VFPU is its flexibility, which allows quick adaptation of the software to the potential changes produced in both the system and the user requirements. The algorithm was tested over a public database that contains the utterances of different users acquired under different environmental conditions, providing good recognition rates.

Implementation on MicroBlaze of AES algorithm to reveal fake keys against side-channel attacks

This paper presents a new proposal for hiding the cryptographic key, when the so-called side-channel attacks (SCAs) are applied to break the security of AES-128. The algorithm was executed on MicroBlaze, but the proposed method is generic and can be extended to any other microprocessor. SCAs are based on examining the correlation produced between the data and operations performed by the microprocessor and its actual power consumption. Traditionally, such weakness is counteracted by introducing countermeasures addressed to reduce as much as possible this correlation, making data and power consumption independent. On the contrary, the proposal presented in this paper introduces some modifications in the AES algorithm. These changes aim at concealing the true key by reinforcing the correlation coefficient in such a way that a classical attack leads to a false key. This way, the system misleads the attacker and apparently behaves as an unprotected system that, in fact, reveals a false positive. The complete system was built on a Virtex-5 FPGA. Experimental results show the strength of our implementation, which is capable of successfully hiding the true cryptographic key.

A Technique for Detecting Materials Characteristics using Mechanical Impacts and a Multilayer Neural Network

In this paper, we propose a method for detecting the characteristics of different materials that have similar properties, by classifying their responses when impacted with small hard spheres. First, a signal conditioning and data compression stage are described. Then a multilayer neural network is used to detect the individual patterns of the samples, and classify the signal. The results of this study indicate that it is possible to identify different materials propertied when the signals are correctly acquired and preprocessed, and the network is adequately trained.

Floating-point accelerator for biometric recognition on FPGA embedded systems

Abstract This paper aims at presenting a Floating-Point Biometric Accelerator (FPBA) specially designed to speed-up processing kernels used in biometric algorithms. The FPBA was developed in order to facilitate its inclusion as part of an embedded system that was implemented on a low-cost FPGA family from Xilinx. The advantage of this approach is that such algorithms can be programmed on the same hardware architecture following a software design flow. The internal design includes several blocks that compute basic operations and transcendental functions useful in biometrics. For comparison purposes, the execution time of four typical biometric kernels resolved by the FPBA were compared against the floating-point unit (FPU) provided by Xilinx. In all cases, the experimental results show that the FPBA reduces the execution time by a factor ranging from x7 to x22. The results also show the execution of two biometric recognition algorithms that are accelerated by x7 and x16.