Mariko Takayanagi

Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond

FinFET integration challenges and solutions are discussed for the 22 nm node and beyond. Fin dimension scaling is presented and the importance of the sidewall image transfer (SIT) technique is addressed. Diamond-shaped epi growth for the raised source-drain (RSD) is proposed to improve parasitic resistance (Rpara) degraded by 3-D structure with thin Si-body. The issue of Vt -mismatch is discussed for continuous FinFET SRAM cell-size scaling.

Effects of nitrogen in HfSiON gate dielectric on the electrical and thermal characteristics

The effects of the nitrogen in the HfSiON gate dielectric on the electrical and thermal properties of the dielectric were investigated. It is clearly demonstrated that nitrogen enhances the dielectric constant of silicates. High dielectric constants of the HfSiON are maintained and boron penetration is substantially suppressed in the HfSiON during high temperature annealing. These properties are ascribed to the homogeneity of the bond structure in the film containing nitrogen through high temperature annealing.

A 0.063 µm 2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

We demonstrate the smallest FinFET SRAM cell size of 0.063 µm2 reported to date using optical lithography. The cell is fabricated with contacted gate pitch (CPP) scaled to 80 nm and fin pitch scaled to 40 nm for the first time using a state-of-the-art 300 mm tool set. A unique patterning scheme featuring double-expose, double-etch (DE2) sidewall image transfer (SIT) process is used for fin formation. This scheme also forms differential fin pitch in the SRAM cells, where epitaxial films are used to merge only the tight pitch devices. The epitaxial films are also used for conformal doping of the devices, which reduces the external resistance significantly. Other features include gate-first metal gate stacks and transistors with 25 nm gate lengths with excellent short channel control.

High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing

Gate-first integration of band-edge (BE) high-κ/metal gate nFET devices with dual stress liners and silicon-on-insulator substrates for the 45nm node and beyond is presented. We show the first reported demonstration of improved short channel control with high-κ/metal gates (HK/MG) enabled by the thinnest Tinv (≪12Å) for BE nFET devices to-date, consistent with simulations showing the need for ≪14Å Tinv at Lgate≪35nm. We report the highest BE HK/MG nFET Idsat values at 1.0V operation. We also show for the first time BE high-κ/metal gate pFETs fabricated with gate-first high thermal budget processing with thin Tinv (≪13Å) and low Vts appropriate for pFET devices. The reliability in these devices was found to be consistent with technology requirements. Integration of high-κ/metal gate nFETs into CMOS devices yielded large SRAM arrays.

Experimental Evidence of Inversion-Layer Mobility Lowering in Ultrathin Gate Oxide Metal-Oxide-Semiconductor Field-Effect-Transistors with Direct Tunneling Current

In this paper, the results of the direct measurement of inversion-layer mobility for metal-oxide-semiconductor field-effect-transistors (MOSFETs) with ultrathin gate oxides, based on the split C–V method are reported. It was demonstrated that inversion-layer electron mobility can be accurately measured for MOSFETs with gate oxide thickness of down to 1.5 nm by the split C–V method with modified measurement of drain conductance under optimum device size and measurement conditions. It was found that, when gate oxide thickness is less than 3 nm, the mobility deceases in the low surface carrier concentration (effective field) region with a decrease in gate oxide thickness and that this mobility lowering becomes smaller in the higher surface carrier concentration (effective field) region. It was also found that mobility limited by some additional scattering observed in thin gate oxides has almost no surface carrier concentration dependence.

High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide

35 nm gate length CMOS devices with oxynitride gate dielectric and Ni SALICIDE have been fabricated to study the feasibility of achieving high performance with gate length scaling. The nitrogen profile in the gate oxynitride was optimized to reduce gate current and to prevent boron penetration in the pFET. The thermal budget in MOL & BEOL processes was reduced to realize shallower junction depth in the S/D extension region and to suppress gate poly-Si depletion. Finally, current drives of 676 /spl mu/A//spl mu/m in nFET and 272 /spl mu/A//spl mu/m in pFET at V/sub dd/ = 0.85 V (I/sub off/ = 100 nA//spl mu/m) were achieved, which are the best values in 35 nm gate length CMOS reported to date.

Demonstration of highly scaled FinFET SRAM cells with high-κ/metal gate and investigation of characteristic variability for the 32 nm node and beyond

Highly scaled FinFET SRAM cells, of area down to 0.128 m2, were fabricated using high-kappa dielectric and a single metal gate to demonstrate cell size scalability and to investigate Vt variability for the 32 nm node and beyond. A single-sided ion implantation (I/I) scheme was proposed to reduce Vt variation of Fin-FETs in a SRAM cell, where resist shadowing is a great issue. In the 0.187 m2 cell, at Vd = 0.6 V, a static noise margin (SNM) of 95 mV was obtained and stable read/write operations were verified from N-curve measurements. sigmaVt of transistors in 0.187 m2 cells was measured with and without channel doping and the result was summarized in the Pelgrom plot. With the 22 nm node design rule, FinFET SRAM cell layouts were compared against planar-FET SRAM cell layouts. An un-doped FinFET SRAM cell was simulated to have significant advantage in read/write margin over a planar-FET SRAM cell, which would have higher sigmaVt mainly caused by heavy doping into the channel region.

High-resolution characterization of ultrashallow junctions by measuring in vacuum with scanning spreading resistance microscopy

The spatial resolution of scanning spreading resistance microscopy has been limited by using conventional probes when measuring in air. Sufficient electric contact of a probe-sample has been difficult to obtain in air due to the existence of moisture/contamination. Two-dimensional carrier profiling of nanoscale silicon devices is performed in a vacuum with conventional probes, and a high spatial resolution is obtained. Ultrashallow junctions down to 10nm are measured accurately with high reproducibility. Experimental results show that a good electric contact between probe and sample is important for obtaining high spatial resolution.

Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond

We present UTBB devices with a gate length (L<inf>G</inf>) of 25nm and competitive drive currents. The process flow features conventional gate-first high-k/metal and raised source/drains (RSD). Back bias (V<inf>bb</inf>) enables V<inf>t</inf> modulation of more than 125mV with a V<inf>bb</inf> of 0.9V and BOX thickness of 12nm. This demonstrates the importance and viability of the UTBB structure for multi-V<inf>t</inf> and power management applications. We explore the impact of GP, BOX thickness and V<inf>bb</inf> on local V<inf>t</inf> variability for the first time. Excellent A<inf>Vt</inf> of 1.27 mV·µm is achieved. We also present simulations results that suggest UTBB has improved scalability, reduced gate leakage (I<inf>g</inf>) and lower external resistance (R<inf>ext</inf>), thanks to a thicker inversion gate dielectric (T<inf>inv</inf>) and body (T<inf>si</inf>) thickness.

Characterization of inversion-layer capacitance of holes in Si MOSFET's

Inversion-layer capacitance (C/sub inv/) in p-channel Si MOSFETs is studied experimentally and theoretically with emphasis on the surface carrier concentration (N/sub s/) dependence, which is important in the quantitative description and the physical understanding. The amount of C/sub inv/ and its influence on the gate capacitance are compared between electron and hole inversion layers. It is experimentally verified that, under same physical thickness of gate oxides, the electrical gate oxide thickness, determined from the gate capacitance, is larger for inversion-layer holes than that for inversion-layer electrons, because of smaller values of C/sub inv/ for inversion-layer holes. Self-consistent Poisson-Schrodinger calculation of C/sub inv/ is performed on basis of the approximation of a constant effective mass and is compared with the experimental C/sub inv/. It is found that the calculation using the effective masses at the valence band edge can accurately represent the experimental results over a whole range of N/sub s/.