Mario Barbareschi

An FPGA-Based Smart Classifier for Decision Support Systems

In recent years, the accuracy and performance of decision support systems have become a bottleneck in many monitoring applications. As for the accuracy, different classification algorithms are available but the overall performance are related to the specific software implementation. In this paper we propose a novel hardware implementation to fasten a decision tree classifier. We also present the evaluation of our architecture by putting in evidence the positive performance results obtained with the proposed implementation.

Secure distribution infrastructure for hardware digital contents

Field-programmable gate array (FPGA) reconfigurability creates the possibility of distributing hardware cores pretty much like software digital contents, possibly on payment or on a subscription basis. In this work, the authors propose an infrastructure for the secure distribution of such hardware digital contents (HDCs). Aimed at the practical realisation of the envisioned scenario, this study analyses the security-related features of the current FPGA devices, for example, (partial) bitstream encryption, and takes them as the underlying constraints for the definition of the infrastructure. This work clearly identifies the roles involved in the secure distribution process, including a trusted third-party entity, and introduces a cryptographic protocol ensuring the confidentiality and the trustworthiness of partial bitstreams dynamically downloaded to the users device. This study also presents a detailed case-study application scenario, namely the secure distribution of image codec components, providing a few quantitative results and demonstrating the limited overhead incurred by the proposed solution in terms of time and area costs. The conclusive section of this study discusses the lesson learned from this work and draws a few proposals for the evolution of security-related FPGA features which may enable the full realisation of the secure HDC distribution concept.

Decision Tree-Based Multiple Classifier Systems: An FPGA Perspective

Combining a hardware approach with a multiple classifier method can deeply improve system performance, since the multiple classifier system can successfully enhance the classification accuracy with respect to a single classifier, and a hardware implementation would lead to systems able to classify samples with high throughput and with a short latency. To the best of our knowledge, no paper in the literature takes into account the multiple classifier scheme as additional design parameter, mainly because of lack of efficient hardware combiner architecture.

Malicious traffic analysis on mobile devices: a hardware solution

The security of smartphone devices is increasingly jeopardised by viruses, intrusion attempts and trojans, which most of them come from the internet traffic. Since the involved traffic is huge and has a complex nature, those threats are difficult to discover and immunise. The mobile devices cannot adopt classical approaches to improve security, such as the traffic analysis, because they are mobile, so resource is constrained and without a power supply. As indeed, most widespread mobile operating systems, such as Android, do not provide any software routine to accomplish this analysis. Recently, in the literature, machine learning approaches have been adopted for the traffic analysis and they exploit a hardware implementation to guarantee high packets throughput and low energy consumption. In order to show the feasibility of the approach, in terms of throughput, latency and energy consumption, in this paper we propose a hybrid computing architecture which enables the communication between the Android OS and a traffic analysis hardware accelerator, coexisting on the same chip. At this aim, the proposed architecture is hosted by new FPGA chip family, the Xilinxs Zynq, a SoPC based on dual-core ARM.

STT-MRAM-Based PUF Architecture Exploiting Magnetic Tunnel Junction Fabrication-Induced Variability

Physically Unclonable Functions (PUFs) are emerging cryptographic primitives used to implement low-cost device authentication and secure secret key generation. Weak PUFs (i.e., devices able to generate a single signature or to deal with a limited number of challenges) are widely discussed in literature. One of the most investigated solutions today is based on SRAMs. However, the rapid development of low-power, high-density, high-performance SoCs has pushed the embedded memories to their limits and opened the field to the development of emerging memory technologies. The Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) has emerged as a promising choice for embedded memories due to its reduced read/write latency and high CMOS integration capability. In this article, we propose an innovative PUF design based on STT-MRAM memory. We exploit the high variability affecting the electrical resistance of the Magnetic Tunnel Junction (MTJ) device in anti-parallel magnetization. We will demonstrate that the proposed solution is robust, unclonable, and unpredictable.

Advancing WSN physical security adopting TPM-based architectures

Cyber Physical Systems typically operate unattended in hostile outdoor environments. A lot of effort has has been made to protect the communication between sensing nodes and the processing infrastructure. However, with regards to physical protection of a node, assessing the integrity of its hardware/software is a challenging issue. In this paper, we propose and evaluate a node architecture which makes use of Trusted Platform Module (TPM) to perform cryptographic operations in a trustworthy manner. TPM builds a chain of trust which enforces a trustability relationship among the nodes components. In such context, the node will function only if all the hardware and software configurations have been verified by means of cryptographic operations. Moreover, using tamper resistant hardware we will ensure that the cryptographic keys do not leave a secure perimeter.

Network Traffic Analysis Using Android on a Hybrid Computing Architecture

Nowadays more and more smartphone applications use internet connection, resulting, from the analysis point of view, in complex and huge generated traffic. Due to mobility and resource limitations, the classical approaches to traffic analysis are no more suitable. Furthermore, the most widespread mobile operating systems, such as Android, do not provide facilities for this task. Novel approaches have been presented in the literature, in which traffic analysis is executed in hardware using the Decision Tree classification algorithm. Although they have been proven to be effective in accelerating the classification process, they typically lack an integration with the remaining system. In order to address this issue, we propose a hybrid computing architecture which enables the communication between the Android OS and a traffic analysis hardware accelerator coexisting on the same chip. To this aim, we provide an Android OS porting on a Xilinx Zynq architecture, composed of a dual-core ARM-based processor integrated with FPGA cells, and define a technique to realize the connection with programmable logic components.

A hardware accelerator for data classification within the sensing infrastructure

Cyber Physical Systems are typically deployed using simple sensing nodes and communicate with a complex elaboration and management infrastructure through the internet. The new trend in the design of such systems is to implement significant part of the data elaboration within the sensing infrastructure. Due to the scarce computing capabilities of the nodes and tight performance constrains, it is necessary to equip the nodes with special purpose hardware accelerators. In particular, we discuss a Decision Support System implementation in which special nodes are able to autonomously perform the data classification task. In this paper, we present a node architecture equipped with a special purpose co-processors to perform data classification trough decision tree visiting algorithm, and we discuss its suitability for the WSN domain.

Testing 90 nm microcontroller SRAM PUF quality

In digital systems, Static Random Access Memories (SRAMs) play an important role since they are available in almost every digital devices and are able to realize Physically Unclonable Functions (PUFs), which can enable security primitives over a wide range of devices without needing additional hardware resources. Indeed, each SRAM presents an unpredictable and unique pattern, established when they are powered-up, which can be useful as key generator and for authentication mechanisms. Before exploiting SRAMs as PUFs, they have to be qualified in terms of stability since the pattern behavior of SRAMs might be heavily influenced by a wide variety of working conditions, such as temperature and applied voltage. In this paper we present the result of an experimental campaign, conducted over real 90nm SRAMs, which aim is to deeply investigate the power-up pattern behavior under different power supply strategies through the PUF quality analysis. In particular we show the reliability, uniqueness and uniformity for SRAMs embedded in STM32F3 and STM32F4 microcontrollers for more than 50 devices.

Implementing Hardware Decision Tree Prediction: A Scalable Approach

Performance of data classification systems is one of the most important aspect when involved data volume, combined with classical computing approaches, does not match tight constraints on latency and throughput. Indeed, even though the classification accuracy of modern machine learning tools is very suitable for the adoption in many applications, they require many computational resources and elaboration time. In the literature, a huge effort has been done to define new architectures and several hardware implementations have been introduced. In this paper, we show a hardware implementation for the classification system based on the Decision Tree and we formally give a demonstration of its scalability in terms of required resources. At the end, with a significant amount of experimental evidences, we prove that the occupied area and power consumption have a linear behavior against the classification parameters.