Mario Kovac

JAGUAR: a fully pipelined VLSI architecture for JPEG image compression standard

In this paper, we describe a fully pipelined single chip VLSI architecture for implementing the JPEG baseline image compression standard. The architecture exploits the principles of pipelining and parallelism to the maximum extent in order to obtain high speed and throughput. The architecture for discrete cosine transform and the entropy encoder are based on efficient algorithms designed for high speed VLSI implementation. The entire architecture can be implemented on a single VLSI chip to yield a clock rate of about 100 MHz which would allow an input rate of 30 frames per second for 1024/spl times/1024 color images. >

SIGMA: a VLSI systolic array implementation of a Galois field GF(2/sup m/) based multiplication and division algorithm

Finite or Galois fields are used in numerous applications like error correcting codes, digital signal processing and cryptography. The design of efficient methods for Galois field arithmetic such as multiplication and division is critical for these applications. A new algorithm based on a pattern matching technique for computing multiplication and division in GF(2/sup m/) is presented. An efficient systolic architecture is described for implementing the algorithm which can produce a new result every clock cycle and the multiplication and division operations can be interleaved. The architecture has been implemented using 2- mu m CMOS technology. The chip yields a computational rate of 33.3 million multiplications/divisions per second. >

E-Health Demystified: An E-Government Showcase

E-health, a priority for governments worldwide, involves multiple stakeholders and requires a complex framework designed for interoperability on legal, organizational, technical, and semantic levels, as the Croatian National Healthcare System exemplifies. Successful implementation suggests a model for e-government more broadly. The first Web extra at http://youtu.be/oB0_80AKUXc is an audio podcast in which Tina Miteko from Tech Talks Central speaks with Benoit Abeloos, Research Program Officer, e-Health for the European Commission, about the progress in e-Health that has been made so far in Europe; the obstacles that need to be surpassed; EU data protection policies; and initiatives that foster entrepreneurship and job growth. Shared via Creative Commons http://creativecommons.org/licenses/by-nc-sa/3.0/legalcode. The second Web extra at http://youtu.be/iN_QscJdMTI is a video in which Ettore Turra and Benoit Abeloos report their vision on e-health in Trentino and in Europe during the First National Workshop: From Personal Notepad to Personal Health Record, held in Trentino on 20-21 March 2014. For more info please visit: https://www.fbk.eu/events/personal-notepad-personal-health-records.

Gradient based selective weighting of neighboring pixels for predictive lossless image coding

Natural, continuous tone images have the very important property of high correlation of adjacent pixels. This property is cleverly exploited in lossless image compression where, prior to the statistical modeling and entropy coding step, predictive coding is used as a decorrelation tool. The use of prediction for the current pixel also reduces the cost of the applied statistical model for entropy coding. Linear prediction, where the predicted value is a linear function of previously encoded pixels (causal template), has proven to give very good results as a decorrelation tool in lossless image compression. We concentrate on adaptive linear predictors used in lossless image coding and propose a new linear prediction method.

Classification and blending prediction for lossless image compression

In this paper we propose a new adaptive prediction scheme based on the blending of multiple static predictors on a dynamically classified causal context of neighboring pixels. The idea of predictor blends is further expanded through the determination of blending context that changes its shape on a pixel-by-pixel basis using a simple classification technique, thus allowing the modeling of more complex image structures such as nontrivially oriented edges, the periodicity and the coarseness of textures. Typical natural images are characterized as being composed of image regions with different local properties. Proposed predictor estimates those properties around the currently unknown pixel and adjusts itself so that the presence of detected properties affects the way final prediction is made

JAGUAR: a high speed VLSI chip for JPEG image compression standard

In this paper, we describe a fully pipelined single chip VLSI architecture for implementing the JPEG baseline image compression standard The architecture exploits the principles of pipelining and parallelism to the maximum extent in order to obtain high speed and throughput. The architecture for discrete cosine transform and the entropy encoder are based on efficient algorithms designed for high speed VLSI implementation. The entire architecture can be implemented on a single VLSI chip to yield a clock rate of about 100 MHz which would allow an input rate of 30 frames per second for 1024/spl times/1024 color images. Currently, a prototype CMOS VLSI chip implementing the proposed architecture is being designed.

A prototype VLSI chip architecture for JPEG image compression

In this paper, we describe the design and implementation of a prototype single chip VLSI architecture for implementing the JPEG baseline image compression standard. The chip exploits the principles of pipelining and parallelism to the maximum extent in order to obtain high speed and throughput. The architecture for discrete cosine transform and the entropy encoder are based on efficient algorithms designed for high speed VLSI implementation. The chip was implemented using the Cadence tools and based on the prototype implementation the proposed chip architecture can yield a clock rate of about 100 MHz which would allow an input rate of 30 frames per second for 1024/spl times/1024 color images.<<ETX>>

System for Secure Data Exchange in Telemedicine

The purpose of this paper is to describe implementation of the system for secure data transfer in telemedicine based on a public key infrastructure. Data security plays a very important role in telemedicine and it is essential to have security issues in mind when designing such a system. System is based on some well known encryption principles, but it also contains new algorithms for medical images compression and it is used in the real medical environment.

ACE: a VLSI chip for Galois field GF(2/sup m/) based exponentiation

In this paper, we present a new algorithm based on a pattern matching technique for computing exponentiations in GF(2/sup m/), for values of m/spl les/8. A systolic array processor architecture has been developed by the authors for performing multiplication and division in GF(2/sup m/). A similar strategy is proposed in this paper for achieving exponentiation at the rate of a new result every clock cycle. A prototype VLSI chip called ACE implementing the proposed algorithm for Galois field GF(2/sup 4/) based exponentiation has been designed and verified using CMOS 2-micron technology. The chip can yield a computational rate of 40 million exponentiations per second.<<ETX>>

A systolic algorithm and architecture for Galois field arithmetic

Finite or Galois fields are used in numerous applications like error correcting codes, digital signal processing and cryptography. The design of efficient methods for Galois field arithmetic such as multiplication and division is critical for these applications. The paper presents a new algorithm for computing multiplication and division in GF(2/sup m/). A systolic architecture is described for implementing the algorithm which can produce a new result every clock cycle. The architecture can be realized as a VLSI chip that can yield a computational rate of 40 million multiplications/divisions per second.<<ETX>>