Marius Enachescu

Nanostructures: a platform for brain repair and augmentation

Nanoscale structures have been at the core of research efforts dealing with integration of nanotechnology into novel electronic devices for the last decade. Because the size of nanomaterials is of the same order of magnitude as biomolecules, these materials are valuable tools for nanoscale manipulation in a broad range of neurobiological systems. For instance, the unique electrical and optical properties of nanowires, nanotubes, and nanocables with vertical orientation, assembled in nanoscale arrays, have been used in many device applications such as sensors that hold the potential to augment brain functions. However, the challenge in creating nanowires/nanotubes or nanocables array-based sensors lies in making individual electrical connections fitting both the features of the brain and of the nanostructures. This review discusses two of the most important applications of nanostructures in neuroscience. First, the current approaches to create nanowires and nanocable structures are reviewed to critically evaluate their potential for developing unique nanostructure based sensors to improve recording and device performance to reduce noise and the detrimental effect of the interface on the tissue. Second, the implementation of nanomaterials in neurobiological and medical applications will be considered from the brain augmentation perspective. Novel applications for diagnosis and treatment of brain diseases such as multiple sclerosis, meningitis, stroke, epilepsy, Alzheimers disease, schizophrenia, and autism will be considered. Because the blood brain barrier (BBB) has a defensive mechanism in preventing nanomaterials arrival to the brain, various strategies to help them to pass through the BBB will be discussed. Finally, the implementation of nanomaterials in neurobiological applications is addressed from the brain repair/augmentation perspective. These nanostructures at the interface between nanotechnology and neuroscience will play a pivotal role not only in addressing the multitude of brain disorders but also to repair or augment brain functions.

VCAM-1 directed target-sensitive liposomes carrying CCR2 antagonists bind to activated endothelium and reduce adhesion and transmigration of monocytes

Chemokines are critically involved in the development of chronic inflammatory-associated diseases such as atherosclerosis. We hypothesized that targeted delivery of compounds to the surface of activated endothelial cells (EC) interferes with chemokine/receptor interaction and thereby efficiently blocks inflammation. We developed PEGylated target-sensitive liposomes (TSL) encapsulating a CCR2 antagonist (Teijin compound 1) coupled with a specific peptide recognized by endothelial VCAM-1 (Vp-TSL-Tj). TSL were characterized for size (by dynamic light scattering), the amount of peptide coupled at the liposomal surface and Teijin release (by HPLC). We report that Vp-TSL-Tj binds specifically to activated EC in vitro and in situ, release the entrapped Teijin and prevent the transmigration of monocytes through activated EC. This is the first evidence that nanocarriers which transport and release chemokine inhibitors at specific pathological sites can reduce chemokine-dependent inflammatory processes.

Towards "zero-energy" using NEMFET-based power management for 3D hybrid stacked ICs

In this paper we describe and evaluate a 3D hybrid power management architecture which makes use of Nano-Electro-Mechanical Field Effect Transistors (NEMFET) as power switches that cut-off the power supply of inactive blocks. 3D stacking combines the appealing extremely low leakage currents of the NanoFETs with the versatility of CMOS technology by allowing for the power switches to be fabricated on a separate die. This simplifies the power planning in general, allows for always-on blocks to also be implemented with NEMFETs, and can increase the computation platform performance because of extra area cleared by the switches. Moreover it leverages the integration of other NEMS/MEMS devices, e.g., energy harvesters, sensors, on the same layer with the power switches. To validate this proposal and evaluate its performance in a real-life scenario we perform a careful assessment of the implications of this hybrid power management architecture on the rest of the system. To this end we consider the 3D embodiment of an embedded openMSP430 processor based SoC platform running a bio-medical sensing application for heart rate detection and measure the effects of the 3D hybrid architecture on sensitive metrics used in power gating designs, e.g., delay degradation, power-up and power-down behavior, and overall energy consumption. Our experiments indicate that, due to the extreme low leakage current of the NEMFETs, the system idle energy is decreased by 2.74x at the expense of a 4x area overhead on the NEMS tier. Moreover, due to the 3D hybrid approach the energy-delay product of the embedded SoC platform is reduced by 9%, with a potential improvement of up to 60% for applications with lower activity, e.g., wireless sensor networks. Last but not least the 3D stacked architecture prevents clock period degradation issues, since the IR Drop is reduced with a factor of 4x. Based on our experiment we believe that such 3D hybrid NEMS/CMOS approach creates the premises for the substantial reduction of an increasingly important component of the total energy consumption, the leakage power while idle, thus it makes nanosystems meet the limited energy budget of local energy harvesters, and become potentially autonomous “zero-energy” devices.

A Molecular Pillar Approach To Grow Vertical Covalent Organic Framework Nanosheets on Graphene: Hybrid Materials for Energy Storage

Hybrid 2D-2D materials composed of perpendicularly oriented covalent organic frameworks (COFs) and graphene were prepared and tested for energy storage applications. Diboronic acid molecules covalently attached to graphene oxide (GO) were used as nucleation sites for directing vertical growth of COF-1 nanosheets (v-COF-GO). The hybrid material has a forest of COF-1 nanosheets with a thickness of 3 to 15 nm in edge-on orientation relative to GO. The reaction performed without molecular pillars resulted in uncontrollable growth of thick COF-1 platelets parallel to the surface of GO. The v-COF-GO was converted into a conductive carbon material preserving the nanostructure of precursor with ultrathin porous carbon nanosheets grafted to graphene in edge-on orientation. It was demonstrated as a high-performance electrode material for supercapacitors. The molecular pillar approach can be used for preparation of many other 2D-2D materials with control of their relative orientation.

Synthesis of single-wall carbon nanotubes by excimer laser ablation

We report the KrF excimer laser ablation of carbonaceous targets in an innovative laser ablation chamber. The targets have been prepared using a new approach, without pressing or hot pressing of the composition. The Co/Ni doped target has yielded single-wall carbon nanotubes with a narrow diameter distribution. High-resolution transmission electron microscopy has been used along with the confocal Raman microscopy to characterize the products obtained. Thermogravimetric analysis confirms the presence of multiple carbonaceous species with different oxidation temperatures.

Ultra low power NEMFET based logic

In this paper, we introduce a Nano-Electro-Mechanical Field Effect Transistor (NEMFET) based logic family tailored to the implementation of low speed and ultra low energy functional units and processors. Basic Boolean gates implemented with NEMFETs only are analysed and compared against equivalent CMOS realisations. Our simulations suggest that the proposed short-circuit current free NEMFET gates exhibit up to 10x dynamic energy reduction and up to 2 orders of magnitude less leakage, at the expense of 10 to 20x slower operation, when compared with CMOS counterparts. We also analyse the fan-in influence on gate performance and observe that NEMFET the gate energy advantage increases with fan-in. Finally, we consider a 3D-Stacked hybrid NEMFET-CMOS computation platform running a heartbeat rate monitor application and demonstrate that NEMFET based logic is an enabling factor for the implementation of “zero-energy” operated systems.

Pulse laser ablation system for carbon nano-onions fabrication

A new laser ablation chamber design for KrF excimer laser synthesis of carbon nanomaterials, including nano-onions, is reported. The conditions for carbon nano-onions deposition, using excimer laser to ablate a commercial pure graphite target, were investigated. The transmission electron microscopy analysis of the collected deposits indicates that mainly nano-onions are obtained when pure graphite targets are ablated. Raman spectroscopy identified without doubt production of carbon nano-onions.

Can SG-FET Replace FET in Sleep Mode Circuits?

The Suspended Gate Field Effect Transistor (SG-FET) appears to have the potential to replace traditional FETs in sleep mode circuits, due to its abrupt switching enabled by electromechanical instability at a certain threshold voltage and its ultra low “off” current(I off ). This paper presents a preliminary assessment of the SG-FET potential if utilized as sleep transistor in real applications, e.g., microprocessors. We first evaluate various SG-FET instances in terms of switching delay, current capability, and leakage. Subsequently, we compare these figures with the ones offered by traditional switch transistors utilized in CMOS technologies. Our simulation results indicate that SG-FET based sleep mode circuits are potentially interesting as they clearly enable substantial leakage reductions due to their extremely low “off” currents (4 orders of magnitude lower than FET) at the expense of a 4x larger active area for the same capability to drive current.

Is TSV-based 3D integration suitable for inter-die memory repair?

In this paper we address lower level issues related to 3D inter-die memory repair in an attempt to evaluate the actual potential of this approach for current and foreseeable technology developments. We propose several implementation schemes both for inter-die row and column repair and evaluate their impact in terms of area and delay. Our analysis suggests that current state-of-the-art TSV dimensions allow inter-die column repair schemes at the expense of reasonable area overhead. For row repair, however, most memory configurations require TSV dimensions to scale down at least with one order of magnitude in order to make this approach a possible candidate for 3D memory repair. We also performed a theoretical analysis of the implications of the proposed 3D repair schemes on the memory access time, which indicates that no substantial delay overhead is expected and that many delay versus energy consumption tradeoffs are possible.

3D stacked wide-operand adders: A case study

In this paper, we address the design of wide-operand addition units in the context of the emerging Through-Silicon Vias (TSV) based 3D Stacked IC (3D-SIC) technology. To this end we first identify and classify the potential of the direct folding approach on existing fast prefix adders, and then discuss the cost and performance of each strategy. Our analysis identifies as a major direct folding drawback the utilization of different structures on each tier. Thus, in order to alleviate this, we propose a novel 3D Stacked Hybrid Prefix/Carry-Select Adder with identical tier structure, which potentially makes the manufacturing of hardware wide-operand adders a reality. Such an N-bit carry select adder can be implemented with K identical tier stacked ICs, where each tier contains two N/K-bit fast prefix adders operating in parallel according to the computation anticipation principle. Their carry-out signals are cascaded through TSVs in order to perform the selection of the sums accordingly, which results in a delay with the asymptotic notation of O(log(N/K) + K). To evaluate the practical implications of direct folding and of the hybrid prefix/carry-select approaches we perform a thorough case study of 65 nm CMOS 3D adder implementations for different operand sizes and number of tiers, and analyze various possible design tradeoffs. Our simulations indicate the hybrid prefix/carry-select approach can achieve speed gains over 3D folding based designs of between 29% and 54%, for 512-bit up to 4096-bit adders, respectively. Even though 3D folding requires less real estate, when considering a more appropriate metric for 3D design, i.e., delay-footprint-cost product, the hybrid prefix/carry-select approach substantially outperforms the folding one and provides delay-footprint-cost reductions between 17.97% and 94.05%.