Marius Evers

Understanding branches and designing branch predictors for high-performance microprocessors

Branch prediction is important in high-performance processors and its importance continues to grow. In the drive for higher execution frequencies, pipelines are lengthened and memory latencies are increased. This increases the cost of branch mispredictions. In this paper we describe some behavior patterns of branches. We believe that understanding the behavior of branches is helpful when designing fetch mechanisms for high-performance microprocessors. We also examine several current branch predictors and discuss how they work. Finally, we look at some of the challenges that we are faced with when designing fetch mechanisms and predictors for future microprocessors and discuss some of the possible solutions.

Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors

A common concern as we scale down transistor threshold voltages while migrating to new process technologies is the requirement to achieve timing closure within a given power budget over various process corners. High performance microprocessors are designed keeping in mind the various process technologies, application space and multi-site fabrication requirements. Described here is an optimization methodology and a unique topology-aware heuristic algorithm employed for high speed microprocessor designs capable of simultaneous threshold voltage selection for library cells across various technology process corners. The algorithm uses knowledge of the circuit topology rather than considering only the immediate local connectivity as is suggested in other heuristic methods and evaluates timing criticalities originating from different input and output logic cones associated with every pin of a failing path. The VTH selection is done so as to affect multiple failing paths with each low VTH cell selection, hence reducing leakage power. Two sets of algorithms are used alternately. One takes advantage of the circuit topology to address multiple failing paths simultaneously. The other performs a fine tuned optimization that has more granularity while considering a particular failing path. This flow is not limited to dual threshold VTH selection but can also support the use of multi-VTH library cells. This flow and its algorithms reduced the usage of low VTH in a particular multi-million transistor design from 35.3% to 10.7% without any loss of performance thus resulting in a 55.6% drop in leakage power. Reducing the usage of lower VTH cells results in significant power reduction. This reduction in power could also allow running the chip at a higher VDD and frequency within the original power envelope. Production results from this tool exceeded the optimization efforts of another commercially used EDA optimization tool.