Mariusz Zdanowski
Warsaw University of Technology
Network
Latest external collaboration on country level. Dive into details by clicking on the dots.
Publication
Featured researches published by Mariusz Zdanowski.
international power electronics and motion control conference | 2012
Jacek Rabkowski; Dimosthenis Peftitsis; Hans-Peter Nee; Mariusz Zdanowski
The paper proposes a novel topology of a simple base drive unit for silicon carbide bipolar junction transistors (BJTs) based on the current-source principle. Energy stored in a small, air-cored inductor is employed to generate a current peak forcing the BJT to turn-on (10–20ns) very rapidly. The driver enables very high switching performance and very low switching losses of the driven BJT. Both the current source and the unit delivering the steady-state current to the base are supplied from the same low-voltage source in order to limit power consumption. Operation principles as well as selected design issues are discussed in the paper and illustrated by experiments. The 1200V/6A SiC BJT driven by the proposed circuit shows a very fast switching speed.
IEEE Transactions on Power Electronics | 2016
Mariusz Zdanowski; Dimosthenis Peftitsis; Szymon Piasecki; Jacek Rabkowski
This paper presents the design process of a 6-kVA quasi-Z-source inverter built with SiC power devices, in particular, employing SiC MOSFETs and SiC Schottky diodes. The main design target is to find the optimal parameters and a good agreement between the efficiency and power density of the converter. The performance of the system may be influenced not only by the switching frequency but also from the specific pulsewidth modulated (PWM) method or type of SiC MOSFET, and, therefore, various design cases are analyzed. At a final step, the 6 kVA/3 × 400 VAC inverter employing the 80 mΩ SiC MOSFETs and operating at 100 kHz with the minimum switching number method is chosen for investigation and a laboratory prototype is built. From experiments, the high performance of the designed system is confirmed. More specifically, it is shown that an efficiency above 95.6% (at 400 VDC, B = 1.9) and a power density higher than 2 kW/dm3 have been reached. Last but not least, the obtained results, which can be recognized as leading in the area of impedance source converters, show the great benefits gained by employing the new power semiconductor devices.
IEEE Transactions on Power Electronics | 2014
Mariusz Zdanowski; Konstantin Kostov; Jacek Rabkowski; R. Barlik; Hans-Peter Nee
The paper presents an inductor with reduced self-capacitance, designed and evaluated with fast-switching SiC transistors in dc-dc converters. A conventional inductor with the same core and number of turns was also build for comparison. The two inductors are tested experimentally on two different 2 kW, 100 kHz dc-dc converters with silicon carbide switches-one with a junction field-effect transistor (JFET) and the other with a bipolar junction transistor (BJT). Replacing the conventional inductor with the one that has lower self-capacitance improved the switching performance of the converter and reduced its electromagnetic emissions. Furthermore, the efficiency of the converter is improved-in the case of the JFET boost converter the power losses were reduced by 16% and by 20% in the case of BJT.
2016 10th International Conference on Compatibility, Power Electronics and Power Engineering (CPE-POWERENG) | 2016
Andrii Chub; Mariusz Zdanowski; Andrei Blinov; Jacek Rabkowski
This paper presents an experimental study of the half-bridge based on high voltage enhancement mode GaN high electron mobility transistors (HEMTs). It was tested with pure inductive load at various switching frequencies and power levels to verify gate driver and cooling system. All tests performed confirm excellent performance of the 650 V GaN HEMTs and the developed half-bridge stage may be applied in future design of the fully controlled DC-DC converter for PV applications.
applied power electronics conference | 2013
Jacek Rabkowski; Dimosthenis Peftitsis; Mariusz Zdanowski; Hans-Peter Nee
This paper describes issues related to design, construction and experimental verification of a 6 kW, 200 kHz boost converter (300 V/600 V) built with four parallel-connected SiC bipolar transistors. The main focus is on parallel-connection of the SiC BJTs: crucial device parameters and influence of the parasitics are discussed. A special solution for the base-drive unit, based on the dual-source driver concept, is also presented in this paper. Experimental verification of the boost converter with special attention to power loss measurement and thermal performance of the parallel-connected transistors is also shown. The peak efficiency measured at nominal conditions was approximately 98.5% where the base-drive unit causes around 10% of the total losses.
international power electronics and motion control conference | 2012
Tomas Modeer; Mariusz Zdanowski; Hans-Peter Nee
Tapped-inductor buck converters can provide large step-down ratios at high efficiency and are well suited in auxiliary power supplies for modular multilevel converter cells supplying gate drive units etc. In this paper the design and testing of three low-leakage tapped inductors for use in a 3kV, 100W buck converter is described.
international symposium on industrial electronics | 2011
Jacek Rabkowski; Mariusz Zdanowski; R. Barlik
The paper presents a concept of the three-phase DC/AC inverter with two impedance networks connected in series (2×Z) built with only Silicon Carbide power devices. Authors describe features of the novel inverter with special attention on serious reduction of voltages on applied Z-network capacitors. Benefits from application of SiC devices: JFETs and Schottky diodes are also discussed. Design and construction of the 2kVA/3×400V RMS laboratory model is shown. Finally, authors prove concept by simulation and experimental tests at 100kHz switching frequency.
international power electronics and motion control conference | 2012
Mariusz Zdanowski; Jacek Rabkowski; Konstantin Kostov; Hans Peter-Nee
In this paper the impact of the parasitic capacitance of the inductor on the performance of a fast-switching boost converters with SiC JFETs is discussed. Two inductor designs, one conventional and another with a space between the winding layers, are investigated and their parasitic capacitances are measured by different methods. The air-gap between the winding layers reduced the inductor self-capacitance more than 8 times. The two inductors were used in a 2 kW, 100 kHz boost converter with a normally-on SiC JFET and their performance was compared. When the inductor with a low self-capacitance was used, there were fewer oscillations during the switching transients and the losses were reduced about 16 %.
Materials Science Forum | 2014
Hans-Peter Nee; Jacek Rabkowski; Dimosthenis Peftitsis; Georg Tolstoy; Juan Colmenares; Diane Sadik; Mietek Bakowski; Jang-Kwon Lim; Antonios Antonopoulos; Lennart Ängquist; Mariusz Zdanowski
The message of this paper is that the silicon carbide power transistors of today are good enough to design converters with efficiencies and switching speeds beyond comparison with corresponding technology in silicon. This is the time to act. Only in the highest power range the devices are missing. Another important step towards high powers is to find new solutions for multi-chip circuit designs that are adapted to the high possible switching speeds of unipolar silicon carbide power transistors.
2016 Progress in Applied Electrical Engineering (PAEE) | 2016
Mariusz Zdanowski; Jacek Rabkowski
This paper presents a study of the GaN HEMT switching features conducted with the use of the half-bridge test converter rated at 2,5 kW. Results of simulation performed in LTSpice are verified by a series of experimental tests at the variable input voltage (up to 400 V) and switching frequency (up to 250 kHz). Three switch scenarios were analyzed: HEMT without the anti-parallel diode, HEMT with an anti-parallel SiC Schottky and HEMT with an additional parallel capacitor. Presented waveforms of drain-source voltage and drain current during switching processes and results of power losses measurements show significant reduction of switching power losses when anti-parallel diode or additional capacitor are applied. Furthermore, an impact of the dead-time length on power losses is also discussed and an optimal choice for assumed parameters of the converter is presented.