Mark B. Ritter

Physics-Based Via and Trace Models for Efficient Link Simulation on Multilayer Structures Up to 40 GHz

Analytical models for vias and traces are presented for simulation of multilayer interconnects at the package and printed circuit board levels. Vias are modeled using an analytical formulation for the parallel-plate impedance and capacitive elements, whereas the trace-via transitions are described by modal decomposition. It is shown that the models can be applied to efficiently simulate a wide range of structures. Different scenarios are analyzed including thru-hole and buried vias, power vias, and coupled traces routed into different layers. By virtue of the modal decomposition, the proposed method is general enough to handle structures with mixed reference planes. For the first time, these models have been validated against full-wave methods and measurements up to 40 GHz. An improvement on the computation speed of at least two orders of magnitude has been observed with respect to full-wave simulations.

120-Gb/s VCSEL-based parallel-optical interconnect and custom 120-Gb/s testing station

A 120-Gb/s optical link (12 channels at 10 Gb/s/ch for both a transmitter and a receiver) has been demonstrated. The link operated at a bit-error rate of less than 10/sup -12/ with all channels operating and with a total fiber length of 316 m, which comprises 300 m of next-generation (OM-3) multimode fiber (MMF) plus 16 m of standard-grade MMF. This is the first time that a parallel link with this bandwidth at this per-channel rate has ever been demonstrated. For the transmitter, an SiGe laser driver was combined with a GaAs vertical-cavity surface-emitting laser (VCSEL) array. For the receiver, the signal from a GaAs photodiode array was amplified by a 12-channel SiGe receiver integrated circuit. Key to the demonstration were several custom testing tools, most notably a 12-channel pattern generator. The package is very similar to the commercial parallel modules that are available today, but the per-channel bit rate is three times higher than that for the commercial modules. The new modules demonstrate the possibility of extending the parallel-optical module technology that is available today into a distance-bandwidth product regime that is unattainable for copper cables.

Specifications of Nanoscale Devices and Circuits for Neuromorphic Computational Systems

The goal of neuromorphic engineering is to build electronic systems that mimic the ability of the brain to perform fuzzy, fault-tolerant, and stochastic computation, without sacrificing either its space or power efficiency. In this paper, we determine the operating characteristics of novel nanoscale devices that could be used to fabricate such systems. We also compare the performance metrics of a million neuron learning system based on these nanoscale devices with an equivalent implementation that is entirely based on end-of-scaling digital CMOS technology and determine the technology targets to be satisfied by these new devices. We show that neuromorphic systems based on new nanoscale devices can potentially improve density and power consumption by at least a factor of 10, as compared with conventional CMOS implementations.

Is 25 Gb/s On-Board Signaling Viable?

What package improvements are required for dense, high-aggregate bandwidth buses running at data rates beyond 10 Gb/s per channel, and when might optical interconnects on the board be required? We present a study of distance and speed limits for electrical on-board module-to-module links with an eye to answering these questions. Hardware-validated models of advanced organic modules and printed circuit boards were used to explore these limits. Simulations of link performance performed with an internal link modeling tool allowed us to explore the effect of equalization and modulation formats at different data rates on link bit error rate and eye opening. Our link models have been validated with active, high-speed differential bus measurements utilizing a 16-channel link chip with programmable equalization and a per-channel data rate of up to 11 Gb/s. Electrical signaling limits were then determined by extrapolating these hardware-correlated models to higher speeds, and these limits were compared to the results of recent work on on-board optical interconnects.

Optical technologies for data communication in large parallel systems

Large, parallel systems have greatly aided scientific computation and data collection, but performance scaling now relies on chip and system-level parallelism. This has happened because power density limits have caused processor frequency growth to stagnate, driving the new multi-core architecture paradigm, which would seem to provide generations of performance increases as transistors scale. However, this paradigm will be constrained by electrical I/O bandwidth limits; first off the processor card, then off the processor module itself. We will present best-estimates of these limits, then show how optical technologies can help provide more bandwidth to allow continued system scaling. We will describe the current status of optical transceiver technology which is already being used to exceed off-board electrical bandwidth limits, then present work on silicon nanophotonic transceivers and 3D integration technologies which, taken together, promise to allow further increases in off-module and off-card bandwidth. Finally, we will show estimated limits of nanophotonic links and discuss breakthroughs that are needed for further progress, and will speculate on whether we will reach Exascale-class machine performance at affordable powers.

Data Center and High Performance Computing Interconnects for 100 Gb/s and Beyond

We review architectures enabling >100 Gb/s interconnects in data centers. Parallel optical interconnects are cost effective for rack to rack interconnects. On-board optical waveguides offer data rate scalability, density and performance advantages over electrical interconnects.

SiGe BiCMOS integrated circuits for high-speed serial communication links

Considerable progress has been made in integrating multi-Gb/s functions into silicon chips for data- and telecommunication applications. This paper reviews the key requirements for implementing such functions in monolithic form and describes their implementation in the IBM SiGe BiCMOS technology. Aspects focused on are the integration of 10-13-Gb/s serializer/deserializer chips with subpicosecond jitter performance, the realization of 40-56-Gb/s multiplexer/demultiplexer functions and clock-and-data- recovery/clock-multiplier units, and, finally, the implementation of some analog front-end building blocks such as limiting amplifiers and electro-absorption modulator drivers. Highlighted in this paper are the key challenges in mixed-signal and analog integrated circuit design at such ultrahigh data rates, and the solutions which leverage high-speed and microwave design and broadband SiGe technologies.

Efficient full-wave modeling of high density TSVs for 3D integration

This paper presents a full-wave electromagnetic approach for modeling the electrical performance of massively-coupled and coated through silicon vias in a sandwiched SiO2-Si-SiO2 substrate. The planar guided wave is analyzed to determine the fundamental mode and high order modes in stratified media. Cylindrical wave expansions and Foldy-Lax equations for multiple scattering techniques are used to efficiently calculate the couplings among the vias. The effect of SiO2 coating around the via is modeled by general T-matrix coefficients. Both silicon loss and copper loss are included in this approach. Numerical simulations of insertion loss, return loss and crosstalk of 1-by-3 and 4-by-4 through silicon via arrays are presented and compared with general-purpose field-solver.

Impedance design for multi-layered vias

This paper presents a methodology based on a semi-analytical scattering model to pre-design the characteristic impedance of multi-layered through hole vias by choosing appropriate via geometrical parameters, dielectric property, and the placement of ground vias. A linear model as a function of design parameters above is further applied to analyze the statistical variation of impedance for different tolerance specification.

Comparison of bandwidth limits for on-card electrical and optical interconnects for 100 Gb/s and beyond

Aggregate chip bandwidths in server and high performance computing have exceeding Tb/s, and if present trends are to continue would lead to doubling the number of signal pins in each generation. For high bandwidth switch and server applications, bandwidth requirements could exceed the package pin limit as early as 2012. We defined metrics to compare the performance of electrical and optical interconnects, which includes bandwidth density (Gb/s/mm2/port), media bandwidth*distance product (GHz*m), power consumption (mW/Gb/s/Port), and technology comparison metric (Gb/s/mm2/port * GHz*m/mW/Port). We will show that optical interconnects offer a performance metric improvement factor of greater than 25 over electrical interconnects.