Mark Gustlin

A Physical Coding Sublayer for 100GbE [Applications & Practice]

This article describes a proposal for the physical coding sublayer (PCS) for the 40-Gb/s and 100-Gb/s Ethernet interfaces currently under standardization within IEEE 802.3. This proposal has been submitted for consideration to the IEEE 802.3 HSSG (High Speed Study Group), but at this writing, no final decision has been made. This article also introduces a novel inverse-multiplexing scheme based on virtual lanes, which allows the PCS to support a wide variety of optical interface technologies (ranging from parallel to serial) and to accommodate advances in electrical signaling technologies (allowing the PCS electrical interface to get narrower and faster over time). The proposed solution applies equally to both 40 Gb/s and 100 Gb/s, but for simplicity this article focuses on the PCS layer and the novel requirements of the 100- Gb/s Ethernet.

System Architecture for 100Gb/s Ethernet; System elements, partition and issues related to 100 gigabit/second Ethernet

This paper explores some of the architectural issues introduced into system design to address the next speed increase for Ethernet interfaces: including system elements, partition, modularity, futureproofing, and high-speed MAC design.