Mark J. Chambers | Researchain

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international solid-state circuits conference | 1996

A 200 Mb/s PRML read/write channel IC

Kaveh Parsi; Robert P. Burns; Alan I. Chaiken; Mark J. Chambers; R. Cheung; B. Forni; David B. Harnishfeger; C. Jam; Scott A. Kaylor; M. Pennell; Jose O. Perez; M. Rohrbaugh; M. Ross; G. Stuhlmiller; N. Weiner

The hard disk drive industry is looking at synchronous design techniques (PRML) with a view to increasing storage density. Currently the high performance commercial read/write channels use (0, 4/4) codes to achieve up to 120 Mb/s data transfer rates. This paper describes a fully integrated read/write channel IC that operates at over 200 Mb/s. The single-chip solution in 0.51 /spl mu/m BiCMOS, has 20 mm/sup 2/ die and uses 0.85 W at 200 Mb/s.

IEEE Journal of Solid-state Circuits | 1996

A PRML read/write channel IC using analog signal processing for 200 Mb/s HDD

Kaveh Parsi; Robert P. Burns; Alan I. Chaiken; Mark J. Chambers; William R. Forni; David B. Harnishfeger; Scott A. Kaylor; Micheal J. Pennell; Jose O. Perez; Narendra Rao; Mark Rohrbaugh; Milk Ross; Gary L. Stuhlmiller

A PR4 read/write IC operating at 50-200 Mb/s while consuming 0.85 W is implemented in 0.5 /spl mu/m BiCMOS technology. The device integrates all of the read/write functions and, in addition, provides a servo demodulator and power management in a single 64-pin TQFP package. PR4 equalization is achieved via a continuous time filter and a 7-tap continuous time transversal equalizer using signed-signed least mean square adaptation.

Archive | 1996