Mark Kennard

FinFET Performance Enhancement with Tensile Metal Gates and Strained Silicon on Insulator (sSOI) Substrate

1. Texas Instruments Inc., SiTD, 13121 TI Boulevard, Dallas, TX USA 2. Dept. of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720 3. Infineon Technologies, Am Campeon 1-12, 85579 Neubiberg, Germany 4. SOITEC S.A., Parc Technologique des Fontaines 38190 Bernin, France 5. Synopsys, Inc., 700 E. Middlefield Road, Mountain View, CA 94043 USA Phone: (510) 643-2639 Fax: (510) 643-2636, E-mail: ksshinweecs.berkeley.edu

Delta-Doping of Epitaxial GaN Layers on Large Diameter Si(111) Substrates

We report on silicon n-type delta (δ)-doping of gallium nitride (GaN) epitaxial layers grown by metalorganic chemical vapor deposition (MOCVD) on silicon (111) substrates. In a series of group III–nitride epitaxial structures a ~1-µm-thick Si bulk-doped GaN layer is replaced by 100, 50, 10, 5, or 1 Si δ-doped planes. While Si bulk-doping of GaN aggrandizes the in-plane tensile stress and the wafer bow with respect to undoped structures, δ-doping is found to reduce both stress and wafer bow. Two-dimensional carrier sheet densities between 1012 and 1013 cm-2 per δ-doped plane and electron mobilities of 1429 cm2 V-1 s-1 are achieved.

Raman spectroscopy study of damage and strain in (001) and (011) Si induced by hydrogen or helium implantation

We use Raman spectrometry to investigate lattice disorder and strain induced by hydrogen or helium implantation in (001) and (011) Si. The phonon peak intensities and the spatial correlation model are used to estimate the amount of damage affecting the phonon coherence length. The redshift due to reduced coherence length is taken into account to fit the model to the experimental spectra. This allows us to correctly estimate a blueshift attributed to a compressive in-plane strain. We observe that the amount of strain increases linearly with the implant dose. For H implants the dependence of strain on crystallographic orientation was discovered. This effect is attributed to the anisotropic morphology of the H-induced extended defects: two-dimensional platelets with preferred orientations versus spherical nanobubbles formed after He implants. Raman results are correlated with the implant damage simulations and compared with the data obtained by other characterization techniques.

Stress Metrology : The challenge for the next generation of engineered wafers

Raman spectroscopy is a powerful and versatile technique for stress measurements in complex stacks of thin crystalline layers at macroscopic and microscopic scales. Using such a technique we show that thick SiGe layers epitaxially grown using graded buffer method are fully relaxed (>95%) at a macroscopic scale but exhibit a small strain modulation at a microscopic scale. For the first time we report the results of Raman micro-mapping of stress distribution in SGOI wafers produced by Smart Cut TM technology. We conclude that Smart Cut TM is a unique method to manufacture the next generation of engineered wafers that can combine strained and/or relaxed SiGe alloys, Si and Ge films, while keeping their initial strain properties at both scales. It is important to develop Raman spectroscopy tool for in-line process control in fabrication of strained Silicon On Insulator (sSOI) wafers.

Multi-Gate MOSFETs with Dual Contact Etch Stop Liner Stressors on Tensile Metal Gate and Strained Silicon on Insulator (sSOI)

This paper describes a comprehensive study of the impact of tCESL (tensile Contact Etch Stop Liner) and cCESL (compressive Contact Etch Stop Liner) on tensile metal gate MuGFET with SOI and globally strained SOI (sSOI) substrates. We have demonstrated that tCESL and cCESL can be effectively used on MuGFETs to provide performance gain. Since tCESL and cCESL affect NMOS and PMOS mobilities in the opposite directions, dual stress liner technology with high-stress cCESL is needed for optimal CMOS MuGFET performance.

Advanced High-Mobility Semiconductor-on-Insulator Materials

Silicon-on-Insulator (SOI) is today the substrate of choice for several applications. In order to boost further circuit performance, new solutions are being explored. In particular, increasing the charge carrier mobility has been identified as a requirement for the next technology nodes. One possible option is to increase transistor channel mobility through local strain engineering via external Stressors, an approach that can be used on bulk silicon as well as standard SOI substrates. Other solutions are based on substrate engineering. The attractiveness of these solutions is largely due to their compatibility with standard CMOS integration processes and architectures and presents the advantage of being independent of transistor geometry. The two approaches can be combined to maximize transistor mobility and on-current. Among the different substrate level approaches, we will focus on three main families: (1) the effect of crystal orientation, (2) strained Si and/or SiGe layers On Insulator, and (3) monocrystalline Ge-On-Insulator substrates.