Mark Richard Nutter

An Open Source Environment for Cell Broadband Engine System Software

The cell broadband engine provides the first implementation of a chip multiprocessor with a significant number of general-purpose programmable cores targeting a broad set of workloads. Open source software played a critical role in the development of the cell software stack. The system includes a power architecture processor and eight attached processor element. The cell team turned to open source software to accelerate the development of an ecosystem for the cell architecture. Using a quadword-based memory interface simplifies the data alignment logic and reduces operation latency.

A study in rapid prototyping: Leveraging software and hardware simulation tools in the bringup of system-on-a-chip based platforms

Traditional use of software and hardware simulators and emulators has been in efforts for chip level analysis and verification. However, prototyping and bringup requirements often demands system or platform level integration and analysis requiring new uses of these traditional pre-silicon methods along with novel interpretations of existing hardware to prototype some functions matching behaviors of future systems. In order to demonstrate the versatility and breadth of the pre-silicon environments in our systems lab, ranging from functional instruction set software simulators to Field Programmable Gate Array (FPGA) chip logic implementations to integrated systems of existing hardware built to mimic key functional aspects of the future platforms, we present our experiences with platform level verification, analysis and early software development/enablement for an I/O attached network appliance system. More specifically, we show how simulation tools along with these early prototype systems were used to do chip level verification, early software development and even system level software testing for a System on a Chip processor attached as an I/O accelerator via Peripheral Component Interconnect Express (PCI Express) to a host system. Our experiences demonstrate that leveraging the full range of pre-silicon environment capabilities results in full system level integrated software test for a I/O attached platform prior to the availability of fully functional ASICs.

ExtraV: boosting graph processing near storage with a coherent accelerator

In this paper, we propose ExtraV, a framework for near-storage graph processing. It is based on the novel concept of graph virtualization, which efficiently utilizes a cache-coherent hardware accelerator at the storage side to achieve performance and flexibility at the same time. ExtraV consists of four main components: 1) host processor, 2) main memory, 3) AFU (Accelerator Function Unit) and 4) storage. The AFU, a hardware accelerator, sits between the host processor and storage. Using a coherent interface that allows main memory accesses, it performs graph traversal functions that are common to various algorithms while the program running on the host processor (called the host program) manages the overall execution along with more application-specific tasks. Graph virtualization is a high-level programming model of graph processing that allows designers to focus on algorithm-specific functions. Realized by the accelerator, graph virtualization gives the host programs an illusion that the graph data reside on the main memory in a layout that fits with the memory access behavior of host programs even though the graph data are actually stored in a multi-level, compressed form in storage. We prototyped ExtraV on a Power8 machine with a CAPI-enabled FPGA. Our experiments on a real system prototype offer significant speedup compared to state-of-the-art software only implementations.