Mark Schaefer

Avoiding Irreducible CSC Conflicts by Internal Communication

Resynthesis of handshake specifications obtained e.g. from BALSA or TANGRAM with speed-independent logic synthesis from STGs is a promising approach. To deal with state-space-explosion, we suggested STG decomposition; a problem is that decomposition can lead to irreducible CSC conflicts. Here, we present a new approach to solve such conflicts by introducing internal communication between the components. We give some first, very encouraging results for very large STGs concerning synthesis time and circuit area.

STG decomposition strategies in combination with unfolding

For synthesising efficient asynchronous circuits one has to deal with the state space explosion problem. In order to alleviate this problem one can decompose the STG into smaller components. This paper deals with the decomposition method of Vogler and Wollowski and introduces several strategies for its efficient implementations. Furthermore, this approach is combined with another method to alleviate state space explosion, which is based on Petri net unfoldings. The developed algorithms are compared by means of benchmark examples, and the experimental results show significant improvement in terms of memory usage and runtime compared with other existing methods.

Component refinement and CSC-solving for STG decomposition

STGs (Signal Transition Graphs) give a formalism for the description of asynchronous circuits based on Petri nets. To overcome the state explosion problem one may encounter during circuit synthesis, a nondeterministic algorithm for decomposing STGs was suggested by Chu and improved by one of the present authors. Here we study how CSC-solving-which is essential for circuit synthesis-can be combined with decomposition. For this purpose, the correctness definition for decomposition is enhanced with internal signals and hierarchical decomposition is proven correct. Based on this, it is shown that speed-independent CSC-solving preserves correctness and can be combined with decomposition. Furthermore, we use our new correctness definition to give the first correctness proof for the decomposition method of Carmona and Cortadella. Finally, we compare three different implementation relations for STGs: one derived from our correctness definition; one defined by Dill based on trace structures; and one derived from I/O-compatibility defined by Carmona and Cortadella.

Strategies for Optimised STG Decomposition

When synthesising an asynchronous circuit from an STG, one often encounters the state explosion problem. In order to alleviate this problem one can decompose the STG into smaller components. This paper deals with the decomposition method of (W. Vogler et al., 2005), (W. Vogler et al., 2002) and introduces several strategies for efficient implementations, proves them correct and compares them by means of benchmark examples

Component refinement and CSC solving for STG decomposition

STGs (Signal Transition Graphs) give a formalism for the description of asynchronous circuits based on Petri nets. To overcome the state explosion problem one may encounter during circuit synthesis, a nondeterministic algorithm for decomposing STGs was suggested by Chu and improved by one of the present authors. We study how CSC solving (which is essential for circuit synthesis) can be combined with decomposition. For this purpose the correctness definition for decomposition is enhanced with internal signals and it is shown that speed-independent CSC solving preserves correctness. The latter uses a more general result about correctness of top-down decomposition. Furthermore, we apply our definition to give the first correctness proof for the decomposition method of Carmona and Cortadella.

Combining decomposition and unfolding for STG synthesis

For synthesising efficient asynchronous circuits one has to deal with the state space explosion problem. In this paper, we present a combined approach to alleviate it, based on using Petri net unfoldings and decomposition. The experimental results show significant improvement in terms of runtime compared with other existing methods.

DESIJ--Enabling Decomposition-Based Synthesis of Complex Asynchronous Controllers

STG-based logic synthesis of complex asynchronous circuits has to deal with state space explosion. To cope with it, a structural STG decomposition --based on transition contraction -- was first proposed by Chu and improved as well as proven correct by Vogler and Wollowski.We present an implementation of this improved version with significant further optimisations, e.g. achieving SI-implementability by internal communication.

Signal transition graph decomposition: internal communication for speed independent circuit implementation

Logic synthesis of speed independent circuits based on signal transition graph (STG) decomposition is a promising approach to tackle complexity problems like state-space explosion. Unfortunately, decomposition can result in components that in isolation have irreducible complete state coding conflicts. In earlier work, the authors showed how to resolve such conflicts by introducing internal communication between components, but only for very restricted specification structures. Here, they improve their former work by presenting algorithms for identifying delay transitions and inserting gyroscopes for specifications having a much more general structure. Thus, the authors are now able to synthesise controllers from real-life specifications. For all algorithms, they present correctness proofs and show their successful application to benchmarks, including very complex STGs arising in the context of control resynthesis.

Avoiding irreducible CSC conflicts by internal communication

Resynthesis of handshake specifications obtained e.g. from BALSA or TANGRAM with speed-independent logic synthesis from STGs is a promising approach. To deal with state-space-explosion, we suggested STG decomposition; a problem is that decomposition can lead to irreducible CSC conflicts. Here, we present a new approach to solve such conflicts by introducing internal communication between the components. We give some first, very encouraging results for very large STGs concerning synthesis time and circuit area.

Output-Determinacy and Asynchronous Circuit Synthesis

Signal Transition Graphs (STG) are a formalism for the description of asynchronous circuit behaviour. In this paper we propose (and justify) a formal semantics of nondeterministic STGs with dummies and OR-causality. For this, we introduce the concept of output-determinacy, which is a relaxation of determinism, and argue that it is reasonable and useful in the speed-independent context. With our theory we improve an STG decomposition algorithm, which can alleviate state explosion.