Mark Van Dal

Germanium p-Channel FinFET Fabricated by Aspect Ratio Trapping

We report scaled Ge p-channel FinFETs fabricated on a 300-mm Si wafer using the aspect-ratio-trapping technique. For long-channel devices, a combination of a trap-assisted tunneling and a band-to-band tunneling leakage mechanism is responsible for an elevated bulk current limiting the OFF-state drain current. However, the latter can be mitigated by device design. We report low long-channel subthreshold swing of 76 mV/decade at VDS=-0.5 V, good short-channel effect control, and high transconductance (gm=1.2 mS/μm at VDS=-1 V and 1.05 mS/μm at VDS=-0.5 V for LG=70 nm). The Ge FinFET presented in this paper exhibits the highest gm/SSsat at VDD=1 V reported for nonplanar unstrained Ge p-FETs to date.

Applications of Ni-based silicides to 45 nm CMOS and Beyond

This paper presents an overview of Ni-alloy (Ni, Ni-Pt and Ni-Ta) silicide development for the 45 nm node and beyond, including applications to self-aligned silicide (SALICIDE) processes, reaction with SiGe and strained Si on SiGe, and applications to fully silicided (FUSI) gates. Key SALICIDE issues addressed include the use of spike or low temperature rapid thermal processes (RTP) to control silicidation and junction leakage on small features, factors affecting the formation of epitaxial pyramidal NiSi 2 grains, and NiSi thermal stability and agglomeration kinetics. Alloying with Pt or Ta is shown to improve thermal stability of NiSi films, although with quite different behaviors. While Pt is incorporated predominantly in solution in NiSi, Ta segregates to the surface of the films. Ni-Pt alloy silicides were also found to achieve low sheet resistance on narrow gates, low contact resistivity and low junction leakage, making them attractive for CMOS applications. For the Ni/SiGe reaction, a narrower RTP process window for low sheet resistance and a lower activation energy for agglomeration were observed when compared to the Ni/Si reaction. The lower thermal stability was correlated to Ge segregation from the Ni(SiGe) films. The Ni/doped poly-Si reaction was studied for FUSI gate applications, showing a retardation of the silicidation kinetics for high B doses and a large pile- up of dopants (for As, B or P) at the NiSi/SiO 2 interface due to dopant snowplow during silicidation. The work function (WF) of NiSi was observed to shift with the addition of dopants, effect attributed to modifications of the interface dipole by the pile-up of dopants. No significant degradation was observed when comparing gate oxide breakdown statistics for Ni FUSI to conventional poly-Si gates. The process window for a FUSI gate-last process (performed after S/D Ni silicidation) was evaluated showing a potential integration problem due to possible degradation of the S/D silicide during the FUSI gate reaction.

High-Performance InAs Gate-All-Around Nanowire MOSFETs on 300 mm Si Substrates

We report on the first realization of InAs n-channel gate-all-around nanowire MOSFETs on 300 mm Si substrates using a fully very large-scale integration (VLSI)-compatible flow. Scaling of the equivalent oxide thickness EOT in conjunction with high-κ dielectric engineering improves the device performance; with an optimized gate stack having an EOT of 1.0 nm, the sub-threshold swing S is 76.8 mV/dec., and the peak transconductance gm is 1.65 mS/μm, at V_ds of 0.5 V, for a gate-all-around nanowire MOSFET having a gate length L_g of 90 nm, a nanowire height H_NW of 25 nm, and a nanowire width W_NW of 20 nm, resulting in Q ≡ gm/S = 21.5, a record for InAs on silicon. Furthermore, we report a source/drain resistance R_sd of 160-200 Ω·μm, amongst the lowest values reported for III-V MOSFETs. Our VLSI-compatible process provides high device yield, which enables statistically reliable extraction of electron transport parameters, such as unidirectional thermal velocity vtx of 3-4×10⁷ cm/s and back-scattering coefficient r_c as a function of gate length.

Doping of sub-50nm SOI layers

Doping of thin body Si becomes very essential topic due to increasing interest of forming source/drain regions in fully depleted planar silicon-on-isolator (SOI) devices or vertical Fin field-effect-transistors (FinFETs). To diminish the role of the short-channel-effect (SCE) control, the Si layers thicknesses target the 10 nm range. In this paper many aspects of thin Si body doping are discussed: dopant retention, implantation-related amorphization, thin body recrystn., sheet resistance (Rs) and carrier mobility in cryst. or amorphized material, impact of the annealing ambient on Rs for various SOI thicknesses. The complexity of 3D geometry for vertical Fin and the vicinity of the extended surface have an impact on doping strategies that are significantly different than for planar bulk devices.

Pre-amorphization and co-implantation suitability for advanced PMOS devices integration

now at Philips Semiconductors, Crolles, France

Atomically flat and uniform relaxed III–V epitaxial films on silicon substrate for heterogeneous and hybrid integration

The integration of III-V semiconductors on silicon (Si) substrate has been an active field of research for more than 30 years. Various approaches have been investigated, including growth of buffer layers to accommodate the lattice mismatch between the Si substrate and the III-V layer, Si- or Ge-on-insulator, epitaxial transfer methods, epitaxial lateral overgrowth, aspect-ratio-trapping techniques, and interfacial misfit array formation. However, manufacturing standards have not been met and significant levels of remaining defectivity, high cost, and complex integration schemes have hampered large scale commercial impact. Here we report on low cost, relaxed, atomically smooth, and surface undulation free lattice mismatched III-V epitaxial films grown in wide-fields of micrometer size on 300 mm Si(100) and (111) substrates. The crystallographic quality of the epitaxial film beyond a few atomic layers from the Si substrate is accomplished by formation of an interfacial misfit array. This development may enable future platforms of integrated low-power logic, power amplifiers, voltage controllers, and optoelectronics components.