Mark White

Impact of junction temperature on microelectronic device reliability and considerations for space applications

The space community and other high reliability users of microelectronic devices have been derating junction temperature and other critical stress parameters for decades to improve device reliability and extend operating life. Semiconductor technology scaling and process improvements, however, compel us to reassess common failure mechanisms and established derating guidelines to provide affirmation that common derating factors remain adequate for current technologies used in high reliability space applications. It is incumbent upon the user to develop an understanding of advanced technology failure mechanisms through modeling, accelerated testing, and failure analysis prior to product insertion in critical applications. This paper provides a summary of an industry survey on junction temperature derating from key microelectronics suppliers, and offers recommendations to users for temperature derating for reliable operation over time. Background information on established derating factors, and recommendations for safe operating junction temperatures for newer technologies are also presented.

A study of scaling effects on DRAM reliability

In this study, commercial 512Mb Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) modules from three progressive technologies — 130nm, 110nm and 90nm — were selected for experimentation to investigate degradation trends as a function of scaling. High temperature, high voltage accelerated stress testing was performed to characterize DRAM reliability and failure rates. Retention time degradation over time as a function of stress was also studied. For each technology generation, two distinct soft error populations were observed: Tail Distribution, characterized by randomly distributed weak bits with Weibull slope =1, and Main Distribution with Weibull slope greater than 1. Retention time was found to degrade exponentially with time. Analysis reveals multiple failure mechanisms are involved in retention tim e degradation. Activation energy was found to change with stress temperature for all three technologies. There are several observations with regard to scaling effects on DRAM reliability. First, the smaller the technology, the larger the operating current increases in percentage after high temperature, high voltage accelerated stress. Second, cell retention time variation decreases as technology scales down. Third, 90nm DRAM has the largest soft-error failure rate among three technologies under equivalent stress, 110nm DRAM has better reliability performance than 130nm at 55°C and 75°C, and 130nm DRAM is the best at 125°C. Studies con tinue into the scaling effects on reliability of progressive DRAM technologies.

A reliability evaluation methodology for memory chips for space applications when sample size is small

This paper presents a reliability evaluation methodology to obtain the statistical reliability evaluation methodology to obtain the statistical reliability information of memory chips for space applications when the test sample size needs to be kept small because of the high cost of the radiation hardness memories. This methodology can be also used to generate overdriving guidelines and characterize production lines in commercial applications and to obtain de-rating guidelines in space applications.

Product Reliability Trends, Derating Considerations and Failure Mechanisms with Scaled CMOS

As microelectronics is scaled into the deep sub-micron regime, space and aerospace users of advanced technology CMOS are reassessing how scaling effects impact long-term product reliability. The effects of electromigration (EM), time-dependent-dielectric-breakdown (TDDB) and hot carrier degradation (HCI and NBTI) wearout mechanisms on scaled technologies and product reliability are investigated, accelerated stress testing across several technology nodes is performed, and FA is conducted to confirm the failure mechanism(s)

Scaled CMOS reliability and considerations for spacecraft systems: Bottom-up and top-down perspectives

The recently launched Mars Science Laboratory (MSL) flagship mission, named Curiosity, is the most complex rover ever built by NASA and is scheduled to touch down on the red planet in August, 2012 in Gale Crater. The rover and its instruments will have to endure the harsh environments of the surface of Mars to fulfill its main science objectives. Such complex systems require reliable microelectronic components coupled with adequate component and system-level design margins. Reliability aspects of these elements of the spacecraft system are presented from bottom-up and top-down perspectives.

Impact of device scaling on deep sub-micron transistor reliability - a study of reliability trends using SRAM

As microelectronics are scaled in to the deep sub-micron regime, users of advanced technology CMOS, particularly in high-reliability applications, should reassess how scaling effects impact long-term reliability. An experimental based reliability study of industrial grade SRAMs, consisting of three different technology nodes, is proposed to substantiate current acceleration models for temperature and voltage life-stress relationships. This reliability study utilizes step-stress techniques to evaluate memory technologies (0.25mum, 0.15mum, and 0.13mum) embedded in many of todays high-reliability space/aerospace applications. Two acceleration modeling approaches are presented to relate experimental FIT calculations to Mfrs qualification data

Qualification of 128 Gb MLC NAND Flash for SMAP space mission

Screening and qualification of a 128 Gb multi-level-cell (MLC) NAND Flash device for the Soil Moisture Passive Active (SMAP) mission (http://smap.jpl.nasa.gov/) is presented here. The MLC technology used in this high density device requires testing above and beyond the typical space test flow.

Cryogenic Reliability Impact on Analog Circuits at Extreme Low Temperatures

Cryogenic temperatures have a greater impact on analog circuit reliability than on digital circuit reliability. Analog gain tolerance may provide a more relaxed criterion while the offset voltage criterion has more bias dependence. For a pre-determined analog circuit offset failure criterion and circuit operating temperature profile, either design rules can be generated for the balanced and unbalanced matching transistor pairs in the circuit for certain hot carrier aging life requirement, or the hot carrier aging life time can be estimated for a certain unbalanced matching transistor pairs/chains