Marko Cupic

Cryptographic Boolean functions

Graphical abstractDisplay Omitted HighlightsAnalysis on the efficiency of EAs when evolving cryptographic Boolean functions.Three fitness functions, four evolutionary algorithms.Wide set of experiments with different algorithm parameter values.The best results are obtained with GP and CGP.We show the problem representation plays a crucial role for reaching top solutions. Boolean functions represent an important primitive in the design of various cryptographic algorithms. There exist several well-known schemes where a Boolean function is used to add nonlinearity to the cipher. Thus, methods to generate Boolean functions that possess good cryptographic properties present an important research goal. Among other techniques, evolutionary computation has proved to be a well-suited approach for this problem. In this paper, we present three different objective functions, where each inspects important cryptographic properties of Boolean functions, and examine four evolutionary algorithms. Our research confirms previous results, but also sheds new insights on the effectiveness and comparison of different evolutionary algorithms for this problem.

A new cost function for evolution of s-boxes

Substitution Boxes (S-Boxes) play an important role in many modern-day cryptographic algorithms, more commonly known as ciphers. Without carefully chosen S-Boxes, such ciphers would be easier to break. Therefore, it is not surprising that the design of suitable S-Boxes attracts a lot of attention in the cryptography community. The evolutionary computation (EC) community also had several attempts using evolutionary paradigms to evolve S-Boxes with good cryptographic properties. This article focuses on a fitness function one should use when evolving highly nonlinear S-Boxes. After an extensive experimental analysis of the current state-of-the-art fitness functions, we present a new one that offers higher speed and better results when compared with the aforementioned fitness functions.

Asynchronous and implicitly parallel evolutionary computation models

This paper presents the design and the application of asynchronous models of parallel evolutionary algorithms. An overview of the existing parallel evolutionary algorithm (PEA) models and available implementations is given. We present new PEA models in the form of asynchronous algorithms and implicit parallelization, as well as experimental data on their efficiency. The paper also discusses the definition of speedup in PEAs and proposes an appropriate speedup measurement procedure. The described parallel EA algorithms are tested on problems with varying degrees of computational complexity. The results show good efficiency of asynchronous and implicit models compared to existing parallel algorithms.

Extension and detailed overview of the HRVFrame framework for heart rate variability analysis

The analysis of heart rate variability (HRV) is an important diagnostic method for detection and assessment of cardiac abnormalities. The availability of complete computer frameworks that can aid researchers in the field of HRV analysis is limited due to the large number of different feature extraction methods. A recently developed framework for feature extraction from cardiac rhythm called HRVFrame is promising, because it allows a user to access more than 40 implemented linear and nonlinear methods. The aim of this paper is to provide a more detailed overview of this framework and all of its capabilities and recent extensions. Additionally, the aim is to encourage the use of HRVFrame as a free and open-source tool for developing medical applications based on Java programming language. A comparison of the framework with existing solutions for cardiac rhythm analysis is provided.

A case study: using multiple-choice tests at university level courses - preparation and supporting infrastructure

In this paper, we will present a case study of using multiple-choice tests for university level courses such as digital logic and artificial intelligence. It is a well known fact that multiple-choice questions can be used to assess students knowledge – not only students recall, but also the verification of students analysis and synthesis abilities. We will give an example of questions for assessment of all three types. We will consider how computers can be used to prepare such tests and what is needed to automatically grade such tests. We will present an open source application that we developed to foster such a process.

A platform independent tool for programming, visualization and simulation of simplified FPGAs

During the last few decades complex programmable circuits have seen a widespread usage in various digital circuit applications. One prominent example are Field Programmable Gate Arrays (FPGAs). Teaching FPGA technology has become an integral part of introductory digital logic courses. However, implementing Boolean functions in this technology requires understanding of several steps that are not trivial, including Boolean function decomposition, mapping the design into physical programmable units and routing. We have developed a portable Java-based tool which allows students to experiment with the required steps for arbitrary Boolean functions and to simulate the obtained implementation. In this paper, we give an overview of the developed tool and discuss its usage in class.

A learning tool for synthesis, visualization, and editing of programming for simple programmable logic devices

Our experiences in teaching digital circuit design at university level indicate that students find it difficult to understand programmable logic devices (PLDs) such as PALs, PLAs, GALs and FPGAs. This is mainly due to the complexity of the topic and the lack of tools that visualize the inner workings of PLDs and enable students to modify and inspect individual components. The majority of publicly available SPLD-related tools are proprietary, platform-specific and do not expose all elements of the PLD structure to the user. In this work, we propose a learning tool that enables synthesis, visualization and editing the programming of a GAL16v8 SPLD. GAL16v8 has been chosen as it is simple enough that its physical implementation can be observed to the smallest detail, while enabling simultaneous realization of multiple Boolean functions. The tool is platform-independent and specifically tailored towards use in an educational setting, facilitating much better understanding of SPLDs through a hands-on experience.