Markus Dietl

A new low power and area efficient semi-digital PLL architecture for low bandwidth applications

Traditional PLL architecture uses one control voltage for both integrated and proportional part of the oscillator. Digital PLL architecture uses 2 control words for integrated and proportional part of the oscillator. In this paper, we describe a new architecture of a Phase lock loop which combines the two approaches and takes the advantages of both.

Low power, small die-size PLL using semi-digital storage instead of big loop filter capacitance

Conventional low bandwidth Phase lock loop uses an external Capacitor together with a big on chip ripple capacitor. A new architecture of a Phase lock loop is proposed which eliminates the need for an external capacitor. Also the value of the on chip capacitor is reduced drastically, reducing the chip size. The PLL architecture proposed uses very low power.

A low power, self-biased, bandwidth tracking semi-digital PLL design

In a conventional charge-pump based PLL design, the loop parameters such as the bandwidth, jitter performance, charge-pump current, pull-in range among others govern the architecture and implementation details of the PLL. Different loop parameter specification change with a change in the reference frequency and in most cases, requires careful re-design of some of the PLL blocks. This paper describes the implementation of a semi-digital PLL for high bandwidth applications, which is self-biased, low-power and exhibits bandwidth tracking for all reference frequencies between 40 MHz and 2.5 GHz in 65nm CMOS technology. This design can be used for a wide range of reference frequencies without redesigning any block. The bandwidth can be fixed to some fraction of the reference frequency during design time. In this work, the PLL is designed to make the bandwidth track 1/20th of the reference frequency. Since this PLL is self-compensated, the PLL performance and the bandwidth remains the same over PVT corners.

Very high bandwidth semi-digital PLL with large operating frequency range

A new method of designing a very high bandwidth semi-digital PLL with a large operating frequency range from 100MHz to 1GHz is proposed. The PLL is modelled in Z-domain. The simulation results is also matched with the modelling to ensure that the PLL is stable for very high bandwidth. The bandwidth achieved is (1 over 4)th of the input reference frequency for the whole operating range mentioned.

Low power and area efficient semi-digital PLL for low bandwidth applications

Conventional low bandwidth Phase lock loop uses an external Capacitor together with a big on chip ripple capacitor. A new architecture of a Phase lock loop is proposed which eliminates the need for an external capacitor. Also the value of the on chip capacitor is reduced drastically, reducing the chip size. The PLL architecture proposed uses very low power.

A BW-tracking semi-digital PLL with near-optimal VCO phase noise shaping in low-cost 0.4 µm CMOS achieving 700 fs rms phase jitter

This paper presents a low-power BW-tracking semi-digital PLL. The design features independently adjustable proportional and integral controller paths. The digital information provided by the storage cells in the I-path are used to let the PLL bandwidth and phase margin track the VCO frequency. The proposed switching scheme in the P-path provides a quiet output in the locked state significantly reducing update jitter. In contrast to classical analog charge pump PLLs, the proposed concept features low design complexity and small area requirements and does not require external components. In contrast to digital PLLs, the proposed architecture allows for an excellent phase noise performance without the need for highly scaled CMOS technologies. As a proof-of-concept of the proposed architecture, a PLL prototype realized in a low cost 0.4 μm CMOS technology is presented, which achieves a measured integrated rms jitter of only 700 fs competing with the state-of-the-art in deep submicron CMOS technologies.

A 2.5 GHz self-compensated, bandwidth tracking PLL with 0.8 ps jitter

In a conventional charge-pump based PLL design, the loop parameters such as the bandwidth, jitter performance, charge-pump current, and pull-in range among others govern the architecture and implementation details of the PLL. Different loop parameter specification change with a change in the reference frequency and in most cases requires careful re-design of some of the PLL blocks. This paper describes the implementation of a semi-digital PLL for high bandwidth applications, which is self-biased, low-power and exhibits bandwidth tracking for all reference frequencies between 40 MHz and 2.5 GHz in 65nm CMOS technology.

A novel approach of cap-sharing to reduce the big loop filter capacitance in semi-digital PLL

With an ever increasing demand of low cost ICs, there is a serious requirement of chips with smaller area and lower power consumption. A new semi-digital PLL architecture was proposed earlier [1], which not only completely removes the off-chip capacitance, but also reduces the required on-chip capacitor value. This paper focuses on modifying this PLL [2, 3] architecture, to reduce the overall on-chip capacitance further by discussing a novel technique of capacitance sharing among the N-semi digital storage cells. PLL using the proposed technique consumes less power and has a smaller chip area.

Cap-sharing technique to reduce on chip capacitance in semi-digital phase lock loops

With an ever increasing demand of low cost ICs, of chips with smaller area and lower power consumption, a new semi-digital PLL architecture was proposed earlier [1]. This paper focuses on modifying this PLL architecture, to reduce the overall on chip capacitance further by discussing a technique of capacitance sharing among the N-semi digital storage cells. PLL using the proposed technique consumes less power and have smaller chip area than their digital counter part.

A novel approach of Cap-sharing to reduce the big loop filter capacitance in semi-digital PLL

With an ever increasing demand of low cost ICs, there is a serious requirement of chips with smaller area and lower power consumption. A new semi-digital PLL architecture was proposed earlier [1], which not only completely removes the off-chip capacitance, but also reduces the required on-chip capacitor value. This paper focuses on modifying this PLL [2, 3] architecture, to reduce the overall on-chip capacitance further by discussing a novel technique of capacitance sharing among the N-semi digital storage cells. PLL using the proposed technique consumes less power and has a smaller chip area.