Markus Myllylä

Complexity Analysis of MMSE Detector Architectures for MIMO OFDM Systems

In this paper, a field programmable gate array (FPGA) implementation of a linear minimum mean square error (LMMSE) detector is considered for MIMO-OFDM systems. Two square root free algorithms based on QR decomposition (QRD) are introduced for the implementation of LMMSE detector. Both algorithms are based on QRD via Givens rotations, namely coordinate rotation digital computer (CORDIC) and squared Givens rotation (SGR) algorithms. Linear and triangular shaped array architectures are considered to exploit (he parallelism in the computations. An FPGA hardware implementation is presented and computational complexity of each implementation is evaluated and compared

Implementation Aspects of List Sphere Detector Algorithms

A list sphere detector (LSD) can be used to approximate the optimal maximum a posteriori (MAP) detection. The total complexity of the LSD algorithms is relative to the number of visited nodes in the search tree. We compare the differences between real and complex signal model in the LSD algorithm implementation and study its impact on the complexity and performance with different search strategies. In hardware implementation, the number of visited nodes needs to be bounded in order to determine the complexity and the latency of the implementation. Thus, we study the performance of LSD algorithms with a limited number of nodes in the search. We show that the algorithms with real signal model are less complex compared to the complex signal model, and that the performance may suffer significantly with limited search depending on the search strategy.

Comparison of Two Novel List Sphere Detector Algorithms for MIMO-OFDM Systems

In this paper, the complexity and performance of two novel list sphere detector (LSD) algorithms are studied and evaluated in multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) system. The LSDs are based on the K-best and the Schnorr-Euchner enumeration (SEE) algorithms. The required list sizes for LSD algorithms are determined for a 2times2 system with 4-quadrature amplitude modulation (QAM), 16-QAM, and 64-QAM. The complexity of the algorithms is compared by studying the number of visited nodes per received symbol vector by the algorithm in computer simulations. The SEE based LSD algorithm is found to be a less complex and a feasible choice for implementation compared to the K-best based LSD algorithm

A List Sphere Detector based on Dijkstra's Algorithm for MIMO-OFDM Systems

A list sphere detector (LSD) based on Dijkstras algorithm, namely increasing radius (IR) - LSD, is introduced for multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) systems. The complexity and the performance of the IR-LSD is compared to a breadth first and depth first search based LSDs. The required list sizes for considered LSDs are determined for a 4times4 system with quadrature amplitude modulations (QAMs). The complexity of the algorithms is relative to the number of visited nodes in the search tree structure. Thus, the algorithm complexities are compared by studying and comparing the number of visited nodes per received symbol vector by the algorithm via computer simulations. The IR-LSD is found to visit the least amount of nodes of the LSDs in the search tree in each studied case, and found the least complex especially with higher order constellations.

The effect of LLR clipping to the complexity of list sphere detector algorithms

The optimal detection for coded system requires the use of a maximum a posteriori (MAP) detection. A list sphere detector (LSD) can be used to approximate the MAP detector. Depending on the used list size, LSD provides a tradeoff between the performance and the computational complexity. The LSD output candidate list is used to calculate the approximation of the probability log-likelihood ratio (LLR) of each transmitted bit. The list should be large enough and it should include at least one candidate for both possible bits for good approximation. The use of a small list size causes inaccurate and, especially, very large LLRs that prevent the decoder from correcting the falsely detected signals and, thus, degrades performance. We study the effect of the LLR clipping to the performance and complexity of the LSD algorithm. We show that by limiting the dynamic range of the LLR the required LSD list size can be decreased, and, thus, the complexity of the algorithms is decreased. The optimal dynamic range values for LLR clipping are determined and the effect of the clipping to the complexity of the LSD algorithms is analyzed.

Implementation aspects of list sphere decoder algorithms for MIMO-OFDM systems

A list sphere decoder (LSD) can be used to approximate the optimal maximum a posteriori (MAP) detector for the detection of multiple-input multiple-output (MIMO) signals. In this paper, we consider two LSD algorithms with different search methods and study some algorithm design choices which relate to the performance and computational complexity of the algorithm. We show that by limiting the dynamic range of log-likelihood ratio, the required LSD list size can be lowered, and, thus, the complexity of the LSD algorithm is decreased. We compare the real and the complex-valued signal models and their impact on the complexity of the algorithms. We show that the real-valued signal model is clearly the less complex choice and a better alternative for implementation. We also show the complexity of the sequential search LSD algorithm can be reduced by limiting the maximum number of checked nodes without sacrificing the performance of the system. Finally, we study the complexity and performance of an iterative receiver, analyze the tradeoff choices between complexity and performance, and show that the additional computational cost in LSD is justified to get better soft-output approximation.

Architecture design and implementation of the increasing radius - List sphere detector algorithm

A list sphere detector (LSD) is an enhancement of a sphere detector (SD) that can be used to approximate the optimal MAP detector. In this paper, we introduce a novel architecture for the increasing radius (IR)-LSD algorithm, which is based on the Dijkstras algorithm. The parallelism possibilities are introduced in the presented architecture, which is also scalable for different multiple-input multiple-output (MIMO) systems. The novel architecture is implemented on a Virtex-IV field programmable gate array (FPGA) chip using high-level ANSI C++ language based Catapult C Synthesis tool from Mentor Graphics. The used word lengths, the latency of the design, and the required resources are presented and analyzed for 4 × 4 MIMO system with 16- quadrature amplitude modulation (QAM). The detector implementation achieves a maximum throughput of 12.1Mbps at high signal-to-noise ratio (SNR).

Fine-grained application-specific instruction set processor design for the K-best list sphere detector algorithm

Very high spectral efficiency and data rates are among the goals of future wireless communication systems. A strong candidate for meeting the requirements is the use of multiple antennas at both the transmitter and the receiver, known as multiple-input multiple-output (MIMO) communications. Sphere detectors have been proposed to be used in MIMO reception to achieve or approximate the optimal maximum likelihood detection with reduced computational complexity. Furthermore, list sphere detectors (LSDs) can be used to approximate the maximum a posteriori detection in channel coded systems. The K-best LSD is a particularly interesting LSD variant with predetermined computational complexity and fixed throughput. In this paper, an application-specific instruction set processor is designed for the K-best LSD using transport triggered architecture. 2 × 2 64-level quadrature amplitude modulation transmission scheme with 16-bit arithmetic and a list size of 16 is used as a baseline design target. List size and word length simulations are presented to justify the choices. The designed processor has a significant amount of general-purpose properties, and it reaches a detection throughput of 7.6 Mbps with a hardware complexity of only 25 000 gate equivalents.

Application-specific Instruction Set Processor Implementation of List Sphere Detector

Multiple-input multiple-output (MIMO) technology enables higher transmission capacity without additional frequency spectrum and is becoming a part of many wireless system standards. Sphere detection has been introduced in MIMO systems to achieve maximum likelihood (ML) or near-ML estimation with reduced complexity. This paper presents an application-specific instruction set processor (ASIP) implementation of if-best list sphere detector (LSD) using the transport triggered architecture (TTA). The implementation is based on using memory and heap data structure for symbol vector sorting. The design space is explored by presenting several variations of the implementation and comparing them with each other in terms of latency and hardware complexity. An early proposal for a parallelized architecture with a detection throughput of approximately 5.3 Mbps is presented.

Application-Specific Instruction Set Processor Implementation of List Sphere Detector

Multiple-input multiple-output (MIMO) technology enables higher transmission capacity without additional frequency spectrum and is becoming a part of many wireless system standards. Sphere detection has been introduced in MIMO systems to achieve maximum likelihood (ML) or near-ML estimation with reduced complexity. This paper reviews related work on sphere detector implementations and presents an application-specific instruction set processor (ASIP) implementation of K-best list sphere detector (LSD) using transport triggered architecture (TTA). The implementation is based on using memory and heap data structure for symbol vector sorting. The design space is explored by presenting several variations of the implementation and comparing them with each other in terms of their latencies and hardware complexities. An early proposal for a parallelized architecture with a decoding throughput of approximately 5.3 Mbps is presented