Markus Olbrich

Analog circuit simulation using range arithmetics

The impact of parameter variations in integrated analog circuits is usually analyzed by Monte Carlo methods with a high number of simulation runs. Few approaches based on interval arithmetic were not successful due to tremendous overapproximations. In this paper, we describe an innovative approach computing transient and DC simulations of nonlinear analog circuits with symbolic range representations that keeps correlation information, and hence has a very limited overapproximation. The methods are based on affine and quadratic arithmetic. Ranges are represented by unique symbols so that linear correlation information is preserved. We demonstrate feasibility of the methods by simulation results using complex analog circuits.

3-D placement considering vertical interconnects

3D integration is going to play an important role in the future. Increasing complexity and increasing impact of interconnects to integrated circuit (IC) performance makes 3D more and more attractive. EDA tools for 3D design hardly exist. We propose a new 3D standard-cell placer based on quadratic programming. It ensures a reduction of the total wirelength and can deal with standard cells and vertical interconnects simultaneously. The final result is a legalized, design rule compliant and discrete 3D placement.

Robust wiring networks for DfY considering timing constraints

In nanometer technologies the importance of opens as yield detractors considerably increases. This requires to reconsider traditional tree based routing approaches for signal wiring. We propose a Greedy Minimum Routing Tree Augmentation (GMRTA) algorithm that shows significantly better results than previous approaches. The algorithm adds links to routing trees, thus increases its robustness against open defects. By exploiting that edges in multiple loops can be removed the augmentation efficiency is further improved. As a special feature, our algorithm keeps timing constraints which have not been considered by previous GMRTA algorithms.

Efficient modeling techniques for dynamic voltage drop analysis

Since the IC technology scales down the effect of voltage drop/ground bounce becomes increasingly significant. Voltage drop and ground bounce can compromise the gate driving capability and degrade the IC performance, and even can cause IC functional failures. Hence, it is crucial to capture this effect efficiently and accurately in order to improve circuit reliability. In this paper, we propose efficient modeling techniques for analyzing power distribution in deep sub micron (DSM) ASIC designs. Current source-based model (CSM) and voltage controlled resistor (VCR) are the key concepts in our approach. A basic prerequisite for the new approach are CMOS standard libraries that are pre-characterized with respect to the corresponding modeling requirements. This paper also presents an approach for this characterization step. The proposed techniques can efficiently handle multiple-input-switching (MIS), including single-input-switching events (SIS) and provide good analysis results compared to the reference with two orders of magnitude speedup, although the cell library pre-characterization is based on SPICE simulations. Our model is independent of the power network context, which implies that different power distribution networks may be analyzed based on the same model and the same cell characterizations. The run-time, memory and accuracy efficiency of the proposed method are demonstrated on an industrial design.

Wirelength Reduction Using 3-D Physical Design

While the feature size of integrated circuits decreases with every technology node, the impact of interconnect delay on the total delay increases. Thus, minimizing the wirelength becomes one of the most important tasks in physical design of high performance circuits.

A methodology for modeling lateral parasitic transistors in smart power ICs

Switching of power stages in smart power ICs, which drive an inductive load, turns on parasitic bipolar transistors and injects minority carriers into the substrate, which can affect the functionality of the chip. In order to evaluate protection measures, these parasitic transistors have to be included into a post layout simulation. In this paper, we present a methodology for automatically generating Verilog-A models for these parasites from layout data. As these models have to account for high injection effects and a distributed current flow, the convergence behavior of this models will be worse than that of classical bipolar models. We found a reasonable trade-off between convergence behavior and accuracy of the model.

Automated generation of hybrid system models for reachability analysis of nonlinear analog circuits

We address the problem of formally verifying nonlinear analog circuits with an uncertain initial set by computing their reachable set. A reachable set contains the union of all possible system trajectories for a set of uncertain states and as such can be used to provably check whether undesired behavior is possible or not. Our method is based on local linearizations of the nonlinear circuit, which naturally results in a piecewise-linear system. To substantially limit the number of required locations, our approach computes linearized locations on-the-fly depending on which states are reachable. We can show that without the proposed on-the-fly technique, the conversion to piecewise-linear systems is infeasible even for a few nonlinear semiconductor devices (discrete state-space explosion problem). Our method is fully automatic and only requires a circuit netlist. Piecewise-linear systems have gained popularity not only for verification, but also for accelerated simulation of nonlinear circuits. Our method provides a guaranteed bound on the number of linearization locations that have to be explicitly computed for such a nonlinear circuit.

Analysis and modeling of minority carrier injection in deep-trench based BCD technologies

This paper proposes a methodology for circuit simulation of parasitic effects caused by minority carrier injection into the substrate of a deep-trench based BCD technology. An equivalent circuit is used containing pre-calculated macro models for the injecting diode, the substrate of the chip and the sensitive diode. The macro models are generated by means of TCAD simulations which determine the carrier density distribution in the substrate. The carrier density in the substrate at the sensitive pn-junction is directly related to the parasitic current of the device. The results of the simulations are verified by test chip measurements.

Fast dynamic power estimation considering glitch filtering

In this paper, we discuss probabilistic simulation techniques used to estimate dynamic power and especially glitch power. Major attention is paid to the problem of modeling inertial delay for using these techniques to estimate switching density at gate level. The inertial delay has a great impact on the glitch power due to filtering effects and is almost impossible to be modeled completely. We propose an approximation algorithm to achieve better accuracy compared to existing approaches. Examples show up to 60% improvement using our solution.

Modeling Lateral Parasitic Transistors in Smart Power ICs

Negative voltages in power stages of junction-isolated Smart Power ICs turn on parasitic bipolar transistors and inject minority carriers into the substrate, which can affect the functionality of the chip. In order to indicate inadmissible substrate currents and to evaluate protection measures, these parasitic transistors have to be included into a postlayout simulation. A methodology has been developed for automatically generating Verilog-A models for these parasites from layout data. These models account for an inhomogeneous current flow and high electron densities in the substrate. A reasonable tradeoff between convergence behavior and accuracy of the model has been found